HD64F3048BF25 Renesas Electronics America, HD64F3048BF25 Datasheet - Page 327

• Manufacturer Part Number: HD64F3048BF25
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048BF25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

9.11.2
Table 9.18 summarizes the registers of port A.
Table 9.18 Port A Registers
Address *
H'FFD1
H'FFD3
Note:
Port A Data Direction Register (PADDR)
PADDR is an 8-bit write-only register that can select input or output for each pin in port A. When
pins are used for TPC output, the corresponding PADDR bits must also be set.
While port A acts as an I/O port, a pin in port A becomes an output pin if the corresponding
PADDR bit is set to 1, and an input pin if this bit is cleared to 0. In modes 3, 4, and 6, PA
fixed at 1 and PA
PADDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PADDR is initialized to H'00 by a reset and in hardware standby mode in modes 1, 2, 5, and 7.
It is initialized to H'80 by a reset and in hardware standby mode in modes 3, 4, and 6. In software
standby mode it retains its previous setting. If a PADDR bit is set to 1, the corresponding pin
maintains its output state in software standby mode.
Bit
Modes
3, 4,
and 6
Modes
1, 2, 5,
and 7
* Lower 16 bits of the address.
Initial value
Read/Write
Initial value
Read/Write
Register Descriptions
Name
Port A data direction
register
Port A data register
7
functions as an address output pin.
PA DDR
7
W
7
1
0
PA DDR
6
W
W
6
0
0
PA DDR
Abbreviation
PADDR
PADR
5
W
W
5
0
0
Port A data direction 7 to 0
These bits select input or output for port A pins
PA DDR
4
W
W
4
0
0
Rev. 3.00 Sep 27, 2006 page 299 of 872
R/W
W
R/W
PA DDR
3
W
W
3
0
0
Modes
1, 2, 5, and 7
H'00
H'00
PA DDR
2
W
W
2
0
0
Initial Value
Section 9 I/O Ports
PA DDR
REJ09B0325-0300
1
W
W
1
0
0
Modes
3, 4, and 6
H'80
H'00
PA DDR
7
DDR is
0
W
W
0
0
0