HD64F3048BF25 Renesas Electronics America, HD64F3048BF25 Datasheet - Page 595
![IC H8 MCU FLASH 128K 100QFP](/photos/12/21/122166/qfp100-g1_pkg_sml.jpg)
HD64F3048BF25
Manufacturer Part Number
HD64F3048BF25
Description
IC H8 MCU FLASH 128K 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.DF3048BF25V.pdf
(903 pages)
Specifications of HD64F3048BF25
Core Processor
H8/300H
Core Size
16-Bit
Speed
8MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3048BF25
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Part Number:
HD64F3048BF25V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
- Current page: 595 of 903
- Download datasheet (5Mb)
16.3
The D/A converter has two built-in D/A conversion circuits that can perform conversion
independently.
D/A conversion is performed constantly while enabled in DACR. If the DADR0 or DADR1 value
is modified, conversion of the new data begins immediately. The conversion results are output
when bits DAOE0 and DAOE1 are set to 1.
An example of D/A conversion on channel 0 is given next. Timing is indicated in figure 16.2.
1. Data to be converted is written in DADR0.
2. Bit DAOE0 is set to 1 in DACR. D/A conversion starts and DA
3. If the DADR0 value is modified, conversion starts immediately, and the result is output after
4. When the DAOE0 bit is cleared to 0, DA
converted result is output after the conversion time. The output value is (DADR0 contents/256)
DAOE0 bit is cleared to 0.
the conversion time.
V
Address
bus
DADR0
DAOE0
DA
Legend:
t
REF
DCONV
0
. Output of this conversion result continues until the value in DADR0 is modified or the
Operation
: D/A conversion time
DADR0
write cycle
High-impedance state
Figure 16.2 Example of D/A Converter Operation
DACR
write cycle
Conversion data 1
t
DCONV
0
becomes an input pin.
Conversion
result 1
DADR0
write cycle
Rev. 3.00 Sep 27, 2006 page 567 of 872
0
t
becomes an output pin. The
DCONV
Conversion data 2
Section 16 D/A Converter
Conversion
result 2
DACR
write cycle
REJ09B0325-0300
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