HD64F3048BF25 Renesas Electronics America, HD64F3048BF25 Datasheet - Page 567

• Manufacturer Part Number: HD64F3048BF25
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048BF25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

The receive margin can therefore be expressed as follows.
Receive margin in smart card mode:
From this equation, if F = 0 and D = 0.5 the receive margin is as follows.
Retransmission
Retransmission is described below for the separate cases of transmit mode and receive mode.
Retransmission when SCI is in Receive Mode (see figure 14.11)
(1) The SCI checks the received parity bit. If it detects an error, it automatically sets the PER
(2) The RDRF bit in SSR is not set to 1 for the error frame.
(3) If an error is not detected when the parity bit is checked, the PER flag is not set in SSR.
(4) If an error is not detected when the parity bit is checked, receiving operations are assumed
(5) When a normal frame is received, at the error signal transmit timing, the data pin is held in
flag to 1. If the RIE bit in SCR is set to the enable state, an ERI interrupt is requested. The
PER flag should be cleared to 0 in SSR before the next parity bit sampling timing.
to have ended normally, and the RDRF bit is automatically set to 1 in SSR. If the RIE bit in
SCR is set to the enable state, an RXI interrupt is requested. If RXI is enabled as a DMA
transfer activation source, the RDR contents can be read automatically. When the DMAC
reads the RDR data, it automatically clears RDRF to 0.
the high-impedance state.
M =
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 372)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute deviation of clock frequency
D = 0.5, F = 0
M = {0.5 – 1/(2
= 49.866%
0.5
2N
1
372)}
(L
100%
0.5) F
D
N
0.5
(1 + F)
Rev. 3.00 Sep 27, 2006 page 539 of 872
100%
Section 14 Smart Card Interface
REJ09B0325-0300