HD64F3048BF25 Renesas Electronics America, HD64F3048BF25 Datasheet - Page 625

• Manufacturer Part Number: HD64F3048BF25
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048BF25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Notes on Using the Boot Mode
1. When this LSI comes out of reset in boot mode, it measures the low period the input at the
2. In boot mode, if any data has been written to the flash memory (if all data is not H'FF), all
3. Interrupts cannot be used during programming or erasing of flash memory.
4.
5. This LSI terminates transmit and receive operations by the on-chip SCI(channel 1) (by clearing
6. Transition to the boot mode executes a reset-start of this LSI after setting the MD
SCI’s RXD
states for this LSI to get ready to measure the low period of the RXD
flash memory blocks are erased. Therefore, this mode should be used for initial on-board
programming, or for forced recovery if the program to be activated in user program mode is
accidentally erased and user program mode cannot be executed, for example.
the RE and TE bits in serial control register (SCR)) before branching to the transmit data
output pin. However, the adjusted bit rate is held in the bit rate register (BRR). At this time, the
TXD
Before branching to the programming control program the value of the general registers in the
CPU are also undefined. Therefore, the general registers must be initialized immediately after
control branches to the programming control program. Since the stack pointer (SP) is
implicitly used during subroutine call, etc., a stack area must be specified for use by the
programming control program.
There are no other internal I/O registers in which the initial value is changed.
FWE, and RXD1 pins according to the mode setting conditions shown in table 18.6.
At this time, this LSI latches the status of the mode pin inside the microcomputer to maintain
the boot mode status at the reset clear (startup from Low level to High level) timing *
To clear boot mode, it is necessary to drive the FWE pin low during the reset, and then execute
reset release *
•
•
The RXD
Before making a transition from the boot mode to the regular mode, the microcomputer
boot mode must be reset by reset input via the RES pin *
hold at low level for at least 20 system clock *
Do not change the input levels at the mode pins (MD
boot mode. When making a mode transition, first enter the reset state by inputting a low
level to the RES pin. When a watchdog timer reset was generated in the boot mode, the
microcomputer mode is not reset and the on-chip boot program is restarted regardless of
the state of the mode pin.
1
is in the high level output state (P9DDR P9
Section 18 ROM (H8/3048F-ONE: Single Power Supply, H8/3048B Mask ROM Version)
1
1
and TXD
pin. The reset should end with RXD
1
. The following points must be noted:
1
pins should be pulled up on the board.
1
2
1
.
high. After the reset ends, it takes about 100
DDR=1, P9DR P9
Rev. 3.00 Sep 27, 2006 page 597 of 872
2
to MD
1
. At this time, the RES pin must be
0
) or the FWE pin while in
1
1
DR=1).
input.
REJ09B0325-0300
0
to MD
1
.
2
,