HD64F3048BF25 Renesas Electronics America, HD64F3048BF25 Datasheet - Page 634

• Manufacturer Part Number: HD64F3048BF25
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048BF25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 18 ROM (H8/3048F-ONE: Single Power Supply, H8/3048B Mask ROM Version)
Rev. 3.00 Sep 27, 2006 page 606 of 872
REJ09B0325-0300
Note: Use a 10 s write pulse for additional programming.
Note: 6. Write Pulse Width
Number of Writes n
Reprogram Data Computation Table
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80.
Original Data
Write pulse application subroutine
Figure 18.13 Program/Program-Verify Flowchart (128-Byte Programming)
Clear PSU bit in FLMCR1
Sub-Routine Write Pulse
1000
(D)
998
999
2. Verify data is read in 16-bit (word) units.
3. Reprogram data is determined by the operation shown in the table below (comparison between the data stored in the program data area and the verify data).
4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional data must be provided in RAM.
5. A write pulse of 30 s or 200 s is applied according to the progress of the programming operation. See Note 6 for details of the pulse widths. When writing of
7. The wait times and value of N are shown in section 21.1.6, Flash Memory Characteristics.
Clear P bit in FLMCR1
10
11
12
13
0
0
1
1
Set PSU in FLMCR1
1
2
3
4
5
6
7
8
9
Set P bit in FLMCR1
Reprogram data storage
Additional-programming
Program data storage
A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
Bits for which the reprogram data is 0 are programmed in the next reprogramming loop. Therefore, even bits for which programming has been completed will be
subjected to programming once again if the result of the subsequent verify operation is NG.
The contents of the reprogram data area and additional data area are modified as programming proceeds.
additional-programming data is executed, a 10 s write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.
Wait (t spsu ) s
Wait (t cpsu ) s
data storage area
Disable WDT
WDT enable
Wait (t sp ) s
Wait (t cp ) s
area (128 bytes)
area (128 bytes)
End Sub
(128 bytes)
RAM
Verify Data
Write Time (tsp) sec
(V)
0
1
0
1
200
200
200
200
200
200
200
200
200
200
30
30
30
30
30
30
Reprogram Data
(X)
*5 *7
*7
*7
*7
1
0
1
1
Start of programming
Programming halted
Programming completed
Programming incomplete;
reprogram
Still in erased state;
no action
Increment
address
Comments
Successively write 128-byte data from additional-
Transfer reprogram data to reprogram data area
programming data area in RAM to flash memory
NG
Additional-programming data computation
Store 128-byte program data in program
data area consecutively to flash memory
Transfer additional-programming data to
Write 128-byte data in RAM reprogram
Write Pulse (Additional programming)
H'FF dummy write to verify address
data area and reprogram data area
additional-programming data area
Reprogram data computation
Clear SWE bit in FLMCR1
Set SWE bit in FLMCR1
Clear PV bit in FLMCR1
Write data = verify data?
verification completed?
Set PV bit in FLMCR1
Start of programming
End of programming
Additional-Programming Data Computation Table
Reprogram Data
Read verify data
Wait (t sswe ) s
Wait (t cswe ) s
Wait (t spvr ) s
Wait (t spv ) s
Wait (t cpv ) s
128-byte data
OK
Write pulse
OK
OK
START
m = 0 ?
6
6
(X')
m= 0
n= 1
0
0
1
1
n ?
n?
OK
OK
Sub-Routine-Call
Sub-Routine-Call
Verify Data
(V)
0
1
0
1
NG
NG
NG
NG
Programming Data (Y)
*7
*4
*1
*7
*7
*2
*4
*3
*4
*7
*1
See Note 6 for pulse width
Additional-
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
0
1
1
1
m = 1
Clear SWE bit in FLMCR1
Programming failure
Wait (t cswe ) s
n
Additional programming
to be executed
Additional programming
not to be executed
Additional programming
not to be executed
Additional programming
not to be executed
N?
OK
Comments
*7
NG
n
n + 1
Reprogram
*7