MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 157

• Manufacturer Part Number: MCF5272CVF66
• Description: IC MPU 32BIT 66MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Not Compliant

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Exception ProcessingPST = 0xC,{PST = 0xB,DD = destination},// stack frame
The PST/DDATA specification for the reset exception is shown below:
Exception ProcessingPST = 0xC,
The initial references at address 0 and 4 are never captured nor displayed since these accesses are treated
as instruction fetches.
For all types of exception processing, the PST = 0xC value is driven at all times, unless the PST output is
needed for one of the optional marker values or for the taken branch indicator (0x5).
Freescale Semiconductor
For JMP and JSR instructions, the optional target instruction address is displayed only for those effective address fields
defining variant addressing modes. This includes the following <ea>x values: (An), (d16,An), (d8,An,Xi), (d8,PC,Xi).
For Move Multiple instructions (MOVEM), the processor automatically generates line-sized transfers if the operand address
reaches a 0-modulo-16 boundary and there are four or more registers to be transferred. For these line-sized transfers, the
operand data is never captured nor displayed, regardless of the CSR value.
The automatic line-sized burst transfers are provided to maximize performance during these sequential memory access
operations.
During normal exception processing, the PST output is driven to a 0xC indicating the exception processing state. The
exception stack write operands, as well as the vector read and target address of the exception handler may also be displayed.
Instruction
wddata.w
wddata.b
wddata.l
rems.l
remu.l
subq.l
subx.l
subi.l
swap
sub.l
sub.l
tst.w
trapf
tst.b
unlk
trap
tst.l
scc
rts
PST = 0x5,{PST = [0x9AB],DD = target}// handler PC
PST = 0x5,{PST = [0x9AB],DD = target} // handler PC
Table 5-22. PST/DDATA Specification for User-Mode Instructions (continued)
Operand Syntax
<ea>y,Dx:Dw
<ea>y,Dx:Dw
{PST = 0xB,DD = destination},// stack frame
{PST = 0xB,DD = source},// vector read
#imm,<ea>x
<ea>y,Rx
Dy,<ea>x
#imm,Dx
MCF5272 ColdFire
<ea>x
<ea>x
<ea>x
<ea>y
<ea>y
<ea>y
Dy,Dx
#imm
Dx
Dx
Ax
PST = 0x1, {PST = 0xB, DD = source operand}
PST = 0x1, {PST = 0xB, DD = source operand}
PST = 0x1, {PST = 0xB, DD = source operand},
PST = 0x5, {PST = [0x9AB], DD = target address}
PST = 0x1
PST = 0x1, {PST = 0xB, DD = source operand}
PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination}
PST = 0x1
PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination}
PST = 0x1
PST = 0x1, {PST = 0x8, DD = source operand}
PST = 0x1, {PST = 0xB, DD = source operand}
PST = 0x1, {PST = 0x9, DD = source operand}
PST = 0x1, {PST = 0xB, DD = destination operand}
PST = 0x4, {PST = 0x8, DD = source operand
PST = 0x4, {PST = 0xB, DD = source operand
PST = 0x1
PST = 0x1
PST = 0x1
PST = 0x4, {PST = 0x9, DD = source operand
®
Integrated Microprocessor User’s Manual, Rev. 3
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PST/DDATA
Debug Support
5-39