MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 410

• Manufacturer Part Number: MCF5272CVF66
• Description: IC MPU 32BIT 66MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Not Compliant

Pulse-Width Modulation (PWM) Module
18.3.2
This register, shown in
greater than or equal to the value in this register, the output is cleared for the remainder of the period. When
the counter overflows, or wraps around, the counter value becomes less than or equal to the value of the
width register and the output is set high.
Writing to the width register while the PWM is enabled will not alter the operation of the PWM until the
end of the current output cycle. That is, the width value is not modified until after the counter has wrapped
around. The PWM must be disabled and then re-enabled to affect its operation before the end of the current
output cycle.
Figure 18-4
18-4
Bits
7–0
PWCRn[CKSL] = 0000: T = 1 x CPU clock period
PWCRn[CKSL] = 1111: T = 32768 x CPU clock period
PWWD[PW] = 0x00
PWWD[PW] = 0x01
PWWD[PW] = 0x80
PWWD[PW] = 0xFF
PWCRn[FRC1] = 1
Name
PW
PWM Width Register (PWWDn)
shows example PWM waveforms and their dependence on PWWD[PW].
Pulse width. Range 0x00–0xFF. When the counter value become greater than PWWD[PW], the output is
cleared for the remainder of the period. When the counter overflows, or wraps around, the counter value
becomes less than or equal to PWWD[PW] and the output is set.
Address
Reset
Field
R/W
MCF5272 ColdFire
Figure
Figure 18-4. PWM Waveform Examples (PWCRn[EN] = 1)
7
MBAR + 0x0D0 (PWWD0); + 0x0D4 (PWWD1); + 0x0D8 (PWWD2)
T
18-3, controls the width of the output pulse. When the counter become
Figure 18-3. PWM Width Register (PWWDn)
Table 18-3. PWWDn Field Descriptions
®
128T
Integrated Microprocessor User’s Manual, Rev. 3
255T
0000_0000
256T
255T
PW
R/W
Description
128T
0
Freescale Semiconductor
T