MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 371

• Manufacturer Part Number: MCF5272CVF66
• Description: IC MPU 32BIT 66MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Not Compliant

16.3.7
The transmitter buffers consist of a 24-byte FIFO and the transmitter shift register. The FIFO accepts
characters from the bus master if the channel’s USRn[TxRDY] is set. A write to the transmitter buffer
clears TxRDY, inhibiting any more characters until the FIFO can accept more data. When the shift register
is empty, it checks if the holding register has a valid character to be sent (TxRDY = 0). If there is a valid
character, the shift register loads it and sets USRn[TxRDY] again. Writes to the transmitter buffer have no
effect when the channel’s TxRDY = 0 and when the transmitter is disabled.
Figure 16-8
16.3.8
The input port change registers (UIPCRn),
CTS.
Table 16-7
Freescale Semiconductor
Bits
7–5
3–1
4
0
Address
Address
Reset
Name
Reset
COS
CTS
Field
Field
R/W
R/W
—
—
describes UIPCRn fields.
UART Transmitter Buffers (UTBn)
UART Input Port Change Registers (UIPCRn)
shows UTBn. TB contains the character in the transmitter buffer.
Reserved, should be cleared.
Change of state (high-to-low or low-to-high transition).
0 No change-of-state since the CPU last read UIPCRn. Reading UIPCRn clears UISRn[COS].
1 A change-of-state longer than 25–50 μs occurred on the CTS input. UACRn can be programmed to generate
Reserved, should be cleared.
Current state. Starting two serial clock periods after reset, CTS reflects the state of CTS. If CTS is detected
asserted at that time, COS is set, which initiates an interrupt if UACRn[IEC] is enabled.
0 The current state of the CTS input is asserted.
1 The current state of the CTS input is negated.
an interrupt to the CPU when a change of state is detected.
7
7
MCF5272 ColdFire
Figure 16-9. UART Input Port Change Registers (UIPCRn)
—
Figure 16-8. UART Transmitter Buffers (UTBn)
Table 16-7. UIPCRn Field Descriptions
®
MBAR + 0x110 (UIPCR0), 0x150 (UIPCR1)
5
Integrated Microprocessor User’s Manual, Rev. 3
Figure
0000_011
MBAR + 0x10C,0x14C
COS
16-9, hold the current state and the change-of-state for
4
0000_0000
Write only
Read only
Description
TB
3
111
1
UART Modules
CTS
CTS
0
0
16-11