MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 39

• Manufacturer Part Number: MCF5272CVF66
• Description: IC MPU 32BIT 66MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Not Compliant

MCF5272 ColdFire
Microprocessor
User’s Manual
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Document Revision History
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© Freescale Semiconductor, Inc., 2005. All rights reserved.
Freescale Semiconductor
Rev. No.
http://www.freescale.com/
2.1
3
Updated to meet Freescale identity guidelines.
• Formatting, layout, spelling, and grammar corrections.
• Corrected the TxFIFO bit description In
• Corrected
• Corrected
• Corrected
• Corrected
MCF5272 ColdFire
UTBn”, is “After being set, this bit is cleared by writing UTBn”).
second SDCLK clock cycle).
asserting on the second SDCLK clock cycle).
second SDCLK clock cycle).
asserting on the second SDCLK clock cycle).
Figure 20-12
Figure 20-16
Figure 20-13
Figure 20-17
®
Integrated Microprocessor User’s Manual, Rev. 3
(OE signal was asserting on the third SDCLK clock cycle, is asserting on the
(OE signal was asserting on the third SDCLK clock cycle, is asserting on the
(R/W and BS signals were asserting on the third SDCLK clock cycle, are
(R/W and BS signals were asserting on the third SDCLK clock cycle, are
®
Integrated
Substantive Change(s)
Table 16-9
(was “Once set, this bit is cleared by reading
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