MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 22

• Manufacturer Part Number: MCF5272CVF66
• Description: IC MPU 32BIT 66MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Not Compliant

Paragraph
Number
13.4 PLIC Register Memory Map ................................................................................................... 13-13
13.5 PLIC Registers ......................................................................................................................... 13-15
13.6 Application Examples .............................................................................................................. 13-35
xxii
13.3.1 Clock Synthesis ............................................................................................................ 13-11
13.3.2 Super Frame Sync Generation ...................................................................................... 13-13
13.3.3 Frame Sync Synthesis ................................................................................................... 13-13
13.5.1 B1 Data Receive Registers (P0B1RR–P3B1RR) ......................................................... 13-15
13.5.2 B2 Data Receive Registers (P0B2RR–P3B2RR) ......................................................... 13-16
13.5.3 D Data Receive Registers (P0DRR–P3DRR) .............................................................. 13-16
13.5.4 B1 Data Transmit Registers (P0B1TR–P3B1TR) ......................................................... 13-17
13.5.5 B2 Data Transmit Registers (P0B2TR–P3B2TR) ........................................................ 13-17
13.5.6 D Data Transmit Registers (P0DTR–P3DTR) ............................................................. 13-18
13.5.7 Port Configuration Registers (P0CR–P3CR) ............................................................... 13-18
13.5.8 Loopback Control Register (PLCR) ............................................................................. 13-20
13.5.9 Interrupt Configuration Registers (P0ICR–P3ICR) ..................................................... 13-20
13.5.10 Periodic Status Registers (P0PSR–P3PSR) ................................................................ 13-22
13.5.11 Aperiodic Status Register (PASR) .............................................................................. 13-23
13.5.12 GCI Monitor Channel Receive Registers (P0GMR–P3GMR) ................................... 13-24
13.5.13 GCI Monitor Channel Transmit Registers (P0GMT–P3GMT) .................................. 13-25
13.5.14 GCI Monitor Channel Transmit Abort Register (PGMTA) ....................................... 13-26
13.5.15 GCI Monitor Channel Transmit Status Register (PGMTS) ....................................... 13-27
13.5.16 GCI C/I Channel Receive Registers (P0GCIR–P3GCIR) .......................................... 13-28
13.5.17 GCI C/I Channel Transmit Registers (P0GCIT–P3GCIT) ......................................... 13-29
13.5.18 GCI C/I Channel Transmit Status Register (PGCITSR) ............................................ 13-30
13.5.19 D-Channel Status Register (PDCSR) ......................................................................... 13-31
13.5.20 D-Channel Request Register (PDRQR) ..................................................................... 13-32
13.5.21 Sync Delay Registers (P0SDR–P3SDR) .................................................................... 13-33
13.5.22 Clock Select Register (PCSR) .................................................................................... 13-34
13.6.1 Introduction .................................................................................................................. 13-35
13.6.2 PLIC Initialization ........................................................................................................ 13-35
13.6.3 Example 1: ISDN SOHO PBX with Ports 0, 1, 2, and 3 .............................................. 13-38
13.6.4 Example 2: ISDN SOHO PBX with Ports 1, 2, and 3 .................................................. 13-40
13.6.5 Example 3: Two-Line Remote Access with Ports 0 and 1 ........................................... 13-41
13.6.2.1 Port Configuration Example ........................................................................... 13-35
13.6.2.2 Interrupt Configuration Example .................................................................... 13-37
MCF5272 ColdFire
Table of Contents (Continued)
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Integrated Microprocessor User’s Manual, Rev. 3
Title
Freescale Semiconductor
Number
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