XR88C681J-F Exar Corporation, XR88C681J-F Datasheet - Page 28

• Manufacturer Part Number: XR88C681J-F
• Description: IC UART CMOS DUAL 44PLCC
• Manufacturer: Exar Corporation
• Type: CMOS Dual Channel UARTr

Specifications of XR88C681J-F

• Number Of Channels: 2, DUART
• Package / Case: 44-LCC (J-Lead)
• Features: *
• Fifo's: 1 Byte, 3 Byte
• Voltage - Supply: 5V
• With Parallel Port: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 1 Mbps
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Supply Current: 15 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 5 V
• Propagation Delay Time Ns: 400 ns
• No. Of Channels: 2
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: PLCC
• No. Of Pins: 44
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1329

CPU, from a external crystal.
Controller is responsible for buffering the bi-directional
Data Bus. Additionally, since the 8080 CPU device does
not directly provide control bus signals, the 8228 Device is
responsible for translating signaling information, from the
8080A device, into the following Control Bus signals; in
order to access memory and peripheral devices.
8080A CPU Module Interrupt Structure
The “Interrupt Structure” of the 8080A CPU is described
here. The 8080A CPU device consists of two signals:
INTE and INT. Additionally, the 8228 Bi-Directional Bus
consists of a single output signal, -INTA.
active-high Interrupt Enable output, and INT is the
active-high Interrupt Request input.
Interrupt” command has been invoked, the INTE output
will be “high” indicating that the 8080 CPU will honor
PHI2 (TTL)
Rev. 2.11
RDYIN
-
TANK
RESIN
+12V
OSC
GND
+5V
Generator
Clock
8224
Figure 6. Schematic of 8080A CPU Module
The 8228 System
+12V
GND
+5V
-5V
If the “Enable
INTE is the
-
STATUS STROBE
HOLD
INT
INTE
WAIT
READY
RESET
SYNC
1
2
8080A CPU
28
-INTA - Interrupt Acknowledge
-MEMR - Memory Read
-MEMW - Memory Write
-IOR - Input Port Read
-IOW - Output Port Write
Figure 6 presents a schematic of the 8080A CPU Module.
interrupt requests from peripherals. Whenever the INT
pin is asserted by a peripheral device requesting an
interrupt, the CPU will complete its current instruction.
After completion of this instruction, the CPU module will
assert -INTA via the 8228 Bi-Directional Bus Driver (U2)
by toggling -INTA “low”. -INTA is the active-low “Interrupt
Acknowledge” signal that the CPU module outputs in
order to initiate the process of interrupt servicing. The
8080A
A0 - A15
-
HDLA
DBIN
BUSEN
-
WR
D0
D1
D2
D3
D4
D5
D6
D7
GND
+5V
CPU
module
Controller
System
8228
only
MEMW
MEMR
supports
INTA
IOW
IOR
D0
D1
D2
D3
D4
D5
D6
D7
“external”