XR88C681J-F Exar Corporation, XR88C681J-F Datasheet - Page 60

• Manufacturer Part Number: XR88C681J-F
• Description: IC UART CMOS DUAL 44PLCC
• Manufacturer: Exar Corporation
• Type: CMOS Dual Channel UARTr

Specifications of XR88C681J-F

• Number Of Channels: 2, DUART
• Package / Case: 44-LCC (J-Lead)
• Features: *
• Fifo's: 1 Byte, 3 Byte
• Voltage - Supply: 5V
• With Parallel Port: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 1 Mbps
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Supply Current: 15 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 5 V
• Propagation Delay Time Ns: 400 ns
• No. Of Channels: 2
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: PLCC
• No. Of Pins: 44
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1329

The oversampling technique mitigates many of the serial
data bit errors by attempting to adjust the receiver
sampling point, to near the midpoint of the bit periods, on a
character to character basis. This approach is successful
for two reasons:
1. It offers periodic correction to the Receiver sampling
2. It limits the Receiver drift phenomenon (between
Therefore, if the user selects to receive data at a baud rate
of 9600 baud; upon detection of the START bit, the
Receiver will begin sampling the data at (9600 x 16) =
153,600Hz.
oversampled up to the 7th 153.6kHz clock pulse, it will
mark this location as the midpoint of the START bit. From
this point on, the 153.6kHz clock signal is divided by 16 to
generate the sample clock (9600Hz) for the remaining
data and overhead bits of the character.
The XR88C681 devices gives the user the option to
declare an external input clock signal as either a 1X or
16X clock signal. Whenever the user is given a choice to
use either the 1X or 16X clock signal (per the Clock Select
Registers), the user is advised to always use the 16X
clock, in order to mitigate the effects of receiver drift. The
user is further advised never to use the 1X clock features
of the DUART, unless the incoming serial data stream is
synchronous with the Receiver (1X) clock.
D.6 Application Examples using the Timing Control
Block
In order to clarify the roles of the assets within the Timing
Control Block, three examples are included.
Example A: Using the BRG
Suppose that the user wishes to receive and transmit data
at a rate of 115.2kbps via Channel A. The user must do
the following:
1. Use a 3.6864 MHz crystal oscillator across the
2. Write 0A
3. Write 08
point.
sampling point adjustments) to typically at most 12 bits
(8 bit character + parity and STOP bits).
X1/CLK and X2 pins; or driving a 3.6864 MHz TTL
signal into the X1/CLK pin (with the X2 pin floating).
the Transmitter BRG Select Extend bit (X = 1).
the Receiver BRG Select Extend bit (X = 1).
Rev. 2.11
16
16
to Command Register A. This step will set
to Command Register A. This step will set
However, once the
Receiver
has
60
4. Write 1xxxxxxxb to ACR This step selects “Bit Rate”
Where the b suffix denotes a binary expression, and x
denotes a “don’t care” value for the binary expression.
5. Write 88
Example B: Programming the Bit Rate via the
Counter/Timer
Suppose the user wishes to transmit and receive data at
62.5kbps via Channel B. Please note that this particular
bit rate is not offered by the BRG. In this case the user can
do the following.
1. Drive a 4 MHz TTL signal into the X1/CLK pin, while
2. Write 00
3. Write 110b to ACR[6:4] This will set the C/T into the
4. Write DD
Thus: Bit Rate = 1 MHz/16 = 62.5kbps.
Example C: Using the External Input Ports
Suppose that, in addition to running Channel B at
62.5kbps (see Example B), he/she wants to Transmit and
Receive data at 1 Mbps via Channel A.
The user needs to perform all of the steps presented in
Example B, along with the following:
1. Write xxxx01xxb to the OPCR (Output Port
This step allows the 1 MHz square wave from the C/T to
be output on OP3.
Note: x = don’t care
The b suffix denotes a binary expression
Set #2 per Table 18 of this data sheet.
Transmit bit rate for Channel A to 115.2kbps (per
Table 17 and Table 18).
the X2 pin is left floating.
results in the C/T generating a square wave of
frequency = 4 MHz/2
Timer mode, and select the Timing source for the C/T
to be the X1/CLK input.
source for the Receiver and Transmitter of Channel B
will be derived from the C/T. Please note that when the
DUART is programmed in this configuration, the C/T
output represents a 16X over sample of the
Transmitted and Received data. Therefore, the chip
circuitry will divide the 1 MHz square wave by 16, just
like for clock signals originating from the BRG.
Configuration Register).
16
16
16
to CSRA. This step sets the Receive and
to CTUR and 02
to CSRB. This will specify that the timing
.
[2] = 1 MHz.
16
to CTLR. This steps