XR88C681J-F Exar Corporation, XR88C681J-F Datasheet - Page 61

• Manufacturer Part Number: XR88C681J-F
• Description: IC UART CMOS DUAL 44PLCC
• Manufacturer: Exar Corporation
• Type: CMOS Dual Channel UARTr

Specifications of XR88C681J-F

• Number Of Channels: 2, DUART
• Package / Case: 44-LCC (J-Lead)
• Features: *
• Fifo's: 1 Byte, 3 Byte
• Voltage - Supply: 5V
• With Parallel Port: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 1 Mbps
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Supply Current: 15 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 5 V
• Propagation Delay Time Ns: 400 ns
• No. Of Channels: 2
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: PLCC
• No. Of Pins: 44
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1329

2. Externally connect the OP3 pin to the IP3 and IP4 pins.
3. Write FF
This step will specify that the timing source for the
Transmitter and Receiver of Channel A will be derived
from input pins IP3 and IP4, respectively. Additionally,
this step allow the DUART hardware to presume that
these input signal are 1X signals. Hence, there is no
division-by-16 of this signal. Therefore, the bit rate of
Channel A is at 1 Mbps.
Please note that if the user were to apply this example,
he/she would be responsible for ensuring that the
Now, here is an explanation for each of these parameters.
D t
The DUART employs dynamic logic throughout much of
its circuitry. Therefore, limits on tCLK and fCLK are
needed in order to ensure that the device will function
properly. This parameter just places a lower limit on the
amount of time at the signal applied through the X1/CLK
pin must reside at the high and low states.
D f
This parameter specifies the range of frequencies
permissible at the X1/CLK input, via either crystal
oscillator or applied TTL input signal. Therefore, the use
can only apply between 2.0 and 4.0 MHz at this input.
Thereby applying a 1 MHz square wave into these two
input pins.
CLK
CLK
Rev. 2.11
f
RTX
f
Symbol
RTX
t
f
t
f
t
f
CTC
CTC
CLK
CLK
RTX
RTX
- X1/CLK (External) High or Low Time
- X1/CLK Crystal High or Low Time
- 16X
- 1X
16
to CSRA.
Parameter
X1/CLK (External) High or Low Time
X1/CLK Crystal or External Frequency
Counter/Timer External Clock High or Low
Time - IP2 Input
Counter/Timer External Clock Frequency - IP2
Input
RXC and TXC (External) High or Low Time -
via IP2, IP3, IP4 and IP5
RXC and TXC (External) Frequency - via IP2,
IP3, IP4, and IP5
16X
1X
Table 20. Clock Timing (Figure 13)
61
incoming serial data stream is synchronous with the 1
MHz (1X) clock signal; in order to minimize bit errors.
D.7 Explanation of Clock Timing Signals
The purpose of this section is to explain the Data Sheet
specification on the Timing Control Block parameters. In
the past, this subject has been the source of considerable
confusion by numerous users.
The XR88C681 Data Sheet presents the following
parameter specifications in the
“AC ELECTRICAL CHARACTERISTICS”
D t
This parameter places a lower limit on the amount of time
that the signal, being applied to the IP2 pin, for use by the
Counter/Timer, can reside at the high and low states.
Please note that this limit has no relationship with the
parameter tRTX, which is another spec associated with
the IP2 input.
D f
This parameter places an upper limit of the input
frequency being applied to the IP2 pin, for use by the
Counter/Timer. The spec basically states that a signal
with frequency up to 4.0 MHz can be applied at the IP2
pin, and still be properly handled by the Counter/Timer.
Time - IP2 Input
IP2 Input
CTC
CTC
Min.
100
100
220
2.0
- Counter/Timer External Clock High or Low
- Counter/Timer External Clock Frequency -
0
0
0
3.6864
Typ.
XR88C681
Max.
4.0
4.0
2.0
1.0
Units
MHz
MHz
MHz
MHz
ns
ns
ns