XR88C681J-F Exar Corporation, XR88C681J-F Datasheet - Page 29

• Manufacturer Part Number: XR88C681J-F
• Description: IC UART CMOS DUAL 44PLCC
• Manufacturer: Exar Corporation
• Type: CMOS Dual Channel UARTr

Specifications of XR88C681J-F

• Number Of Channels: 2, DUART
• Package / Case: 44-LCC (J-Lead)
• Features: *
• Fifo's: 1 Byte, 3 Byte
• Voltage - Supply: 5V
• With Parallel Port: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 1 Mbps
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Supply Current: 15 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 5 V
• Propagation Delay Time Ns: 400 ns
• No. Of Channels: 2
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: PLCC
• No. Of Pins: 44
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1329

vectored-interrupt processing. Hence, when -INTA is
asserted, the CPU module is awaiting “vector”
information on the Data bus. In the case of the 8080A
CPU Module, this “vector” information is typically the
op-code for one of the RESTART instructions (RST). The
8080A CPU supports up to eight different RST
instructions (RST 0 through RST 7). These instructions
are one-byte calls to specific locations within the CPU’s
memory space, where the appropriate interrupt service
routine exists. Table 10 presents a list of these RESTART
instructions, the op-codes, and the corresponding
RESTART address.
Therefore, once the CPU receives the op-code for one of
these RESTART instructions, it will begin executing this
instruction by loading the Program Counter will the
appropriate “Restart Address”.
control will be branched to the “Restart Address” location.
For Example:
If the op-code “E7
the -INTA cycle, this op-code corresponds with the “RST
4” command and, the CPU will load 0020
Program Counter and program control will branch to that
location in memory (see Table 10).
Table 10. 8080A and 8085 CPU Restart Instructions
Op-Code (hex)
Rev. 2.11
CF
DF
C7
D7
E7
EF
FF
F7
Used With Vectored Interrupts
16
” is loaded onto the Data Bus during
Mnemonic
RST 0
RST 1
RST 2
RST 3
RST 4
RST 5
RST 6
RST 7
Afterwards, program
Restart Address
(hex)
0000
0008
0010
0018
0020
0028
0030
0038
16
into the
29
Interfacing the 8080 CPU Module to the XR88C681
DUART for Interrupt Processing
The 8080A CPU can be connected to the XR88C681 and
run in the Interrupt Driven mode. Figure 7 presents an
approach that can be applied to interfacing the
XR88C681 DUART to the 8080A CPU for “external”
vectored interrupt processing. Please note that Figure 8
only includes information pertaining to DUART interrupt
servicing.
Generator, the Address Bus, etc.) have been omitted from
the schematic. In this schematic, the DUART Interrupt
Service Routine is located at 0020
Additionally, the DUART has been configured to operate
in the I-Mode. The function description of this circuit is
presented here.
The XR88C681 will request an interrupt to the 8080A
CPU, by toggling its -INTR output “low”. This signal is
inverted and applied to the active-high INT input of the
CPU. Once the 8080A CPU has completed its current
instruction, it will assert the active-low -INTA signal (from
the 8228 Bi-Directional Bus Driver). At this time, both the
-INTR signal (from the DUART) and the -INTA signal
(from the 8228) are each at a logic “low”. The -INTR and
-INTA signals are both routed to a two-input OR gate.
Hence, when both -INTR and -INTA are at logic “low”, the
output of the OR-gate will also be at a logic “low”, and
thereby asserting both of the Output Enable (OE) inputs
of the SN74LS244 Data Bus buffer (U3). This “ORing” of
the -INTR and -INTA signals is used to insure that only the
peripheral device requesting the interrupt is the one that
receives the service (e.g., responsive to the asserted
-INTA signal). Once both -OE inputs of U3 are asserted,
the data, applied at the input of this device (U3) will now
appear at the output of this device, and at the D7 - D0
inputs of the 8228 device (U2). Please note that, in this
example, the value “E7
U3. This value is the op-code for the “RST 4” command.
Hence, once this data is gated into the CPU module, via
the data bus, the CPU will load 0020
Counter and branch program control to that location. The
Interrupt Service Routine for the DUART exists at this
location in memory.
Other circuitry (such as the 8224 Clock
16
” is hard-wired into the input of
XR88C681
16
into its Program
16
in memory.