AT91SAM7SE256B-CUR Atmel, AT91SAM7SE256B-CUR Datasheet
AT91SAM7SE256B-CUR
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AT91SAM7SE256B-CUR Summary of contents
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Features ® • Incorporates the ARM7TDMI ARM – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt ™ – EmbeddedICE In-circuit Emulation, Debug Communication Channel Support • Internal High-speed Flash – 512 Kbytes, Organized in Two ...
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... One Four-channel 16-bit PWM Controller (PWMC) • One Two-wire Interface (TWI) – Master, Multi-Master and Slave Mode Support, All Two-wire Atmel EEPROMs Supported – General Call Supported in Slave Mode • One 8-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os ® ...
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... Description Atmel's SAM7SE Series is a member of its Smart ARM Microcontroller family based on the 32- bit ARM7 • SAM7SE512 features a 512 Kbyte high-speed Flash and a 32 Kbyte SRAM. • SAM7SE256 features a 256 Kbyte high-speed Flash and a 32 Kbyte SRAM. • SAM7SE32 features a 32 Kbyte high-speed Flash and an 8 Kbyte SRAM. ...
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Block Diagram Figure 2-1. IRQ0-IRQ1 PCK0-PCK2 VDDFLASH VDDCORE VDDCORE SAM7SE512/256/32 Preliminary 4 SAM7SE512/256/32 Block Diagram Signal Description ICE TDI TDO JTAG TMS SCAN TCK JTAGSEL System Controller TST FIQ Memory Controller AIC Embedded Flash Controller PDC DRXD DBGU DTXD ...
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Signal Description Table 3-1. Signal Description List Signal Name Function Voltage Regulator and ADC Power VDDIN Supply Input VDDOUT Voltage Regulator Output VDDFLASH Flash and USB Power Supply VDDIO I/O Lines Power Supply VDDCORE Core Power Supply VDDPLL PLL ...
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Table 3-1. Signal Description List (Continued) Signal Name Function PA0 - PA31 Parallel IO Controller A PB0 - PB31 Parallel IO Controller B PC0 - PC23 Parallel IO Controller C DDM USB Device Port Data - DDP USB Device Port ...
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Table 3-1. Signal Description List (Continued) Signal Name Function TWD Two-wire Serial Data TWCK Two-wire Serial Clock AD0-AD3 Analog Inputs AD4-AD7 Analog Inputs ADTRG ADC Trigger ADVREF ADC Reference PGMEN0-PGMEN2 Programming Enabling PGMM0-PGMM3 Programming Mode PGMD0-PGMD15 Programming Data PGMRDY Programming ...
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Table 3-1. Signal Description List (Continued) Signal Name Function NANDCS NAND Flash Chip Select Line NANDOE NAND Flash Output Enable NANDWE NAND Flash Write Enable NANDCLE NAND Flash Command Line Enable NANDALE NAND Flash Address Line Enable SDCK SDRAM Clock ...
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Package The SAM7SE512/256/32 is available in: • 128-lead LQFP package with a 0.5 mm lead pitch. • 10x 10 x 1.4 mm 144-ball LFBGA package with a 0.8 mm lead pitch 4.1 128-lead LQFP Package ...
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LQFP Pinout Table 4-1. Pinout in 128-lead LQFP Package 1 ADVREF 33 2 GND 34 3 AD7 35 4 AD6 36 5 AD5 37 6 AD4 38 7 VDDOUT 39 8 VDDIN 40 9 PA20/PGMD8/AD3 41 10 PA19/PGMD7/AD2 ...
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LFBGA Package Outline Figure 4-2 description is given in the Mechanical Characteristics section. Figure 4-2. 6222F–ATARM–14-Jan-11 SAM7SE512/256/32 Preliminary shows the orientation of the 144-ball LFBGA package and a detailed mechanical 144-ball LFBGA Package Outline (Top View ...
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LFBGA Pinout Table 4-2. SAM7SE512/256/32 Pinout for 144-ball LFBGA Package Pin Signal Name Pin A1 PB7 D1 A2 PB8 D2 A3 PB9 D3 A4 PB12 D4 A5 PB13 D5 A6 PB16 D6 A7 PB22 D7 A8 PB23 D8 ...
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Power Considerations 5.1 Power Supplies The SAM7SE512/256/32 has six types of power supply pins and integrates a voltage regulator, allowing the device to be supplied with only one voltage. The six power supply pin types are: • VDDIN pin. ...
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One external 2.2 µF (or 3.3 µF) X7R capacitor should be connected between VDDOUT and GND. Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor ...
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I/O Lines Considerations 6.1 JTAG Port Pins TMS, TDI and TCK are Schmitt trigger inputs. TMS, TDI and TCK do not integrate a pull-up resistor. TDO is an output, driven VDDIO, and has no pull-up resistor. ...
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SDCK Pin The SDCK pin is dedicated to the SDRAM Clock and is an output-only without pull-up. Maximum Output Frequency of this pad is 48 MHz at 3.0V and 25 MHz at 1.65V with a maximum load of 30 ...
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Processor and Architecture 7.1 ARM7TDMI Processor • RISC processor based on ARMv4T Von Neumann architecture – Runs MHz, providing 0.9 MIPS/MHz (core supplied with 1.8V) • Two instruction sets – ARM – Thumb • Three-stage ...
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Individually programmable size between 1K Byte and 1M Byte – Individually programmable protection against write and/or user access – Peripheral protection against write and/or user access • Embedded Flash Controller – Embedded Flash interface three programmable wait ...
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Multiple device adaptability – Compliant with LCD Module – Compliant with PSRAM in synchronous operations – Programmable Setup Time Read/Write – Programmable Hold Time Read/Write • Multiple Wait State Management – Programmable Wait State Generation – External Wait Request ...
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Peripheral DMA Controller • Handles data transfer between peripherals and memories • Eleven channels – Two for each USART – Two for the Debug Unit – Two for the Serial Synchronous Controller – Two for the Serial Peripheral Interface ...
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Memories • 512 Kbytes of Flash Memory (SAM7SE512) – dual plane – two contiguous banks of 1024 pages of 256 bytes – Fast access time, 30 MHz single-cycle access in Worst Case conditions – Page programming time: 6 ms, ...
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Figure 8-1. SAM7SE Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256 MBytes 0x0FFF FFFF 0x1000 0000 EBI Chip Select 0 256 MBytes SMC 0x1FFF FFFF 0x2000 0000 EBI 256 MBytes Chip Select 1/ SMC or SDRAMC 0x2FFF FFFF ...
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A first level of address decoding is performed by the Memory Controller, i.e., by the implementa- tion of the Advanced System Bus (ASB) with additional features. Decoding splits the 4G bytes of address space into 16 areas of 256M bytes. ...
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Figure 8-2. Figure 8-3. 8.1.2 Embedded Flash 8.1.2.1 Flash Overview The Flash of the SAM7SE512 is organized in two banks (dual plane) of 1024 pages of 256 bytes. It reads as 131,072 32-bit words. The Flash of the SAM7SE256 is ...
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The Flash benefits from the integration of a power reset cell and from the brownout detector. This prevents code corruption during power supply changes, even in the worst conditions. 8.1.2.2 Embedded Flash Controller The Embedded Flash Controller (EFC) manages accesses ...
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The security bit can only be enabled through the Command “Set Security Bit” of the EFC User Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1 and after a full flash erase is ...
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SAM-BA Boot The SAM-BA Boot is a default Boot Program which provides an easy way to program in-situ the on-chip Flash memory. The SAM-BA Boot Assistant supports serial communication via the DBGU or the USB Device Port. • ...
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System Controller The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset. The System Controller peripherals are all mapped to the highest 4 Kbytes of address space, between addresses 0xFFFF F000 and ...
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Figure 9-1. periph_irq[2..18] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset periph_nreset power_on_reset en BOD POR RCOSC OSC PLL periph_nreset 6222F–ATARM–14-Jan-11 SAM7SE512/256/32 Preliminary System Controller Block Diagram System Controller irq0-irq1 Advanced fiq Interrupt Controller int MCK dbgu_irq Debug force_ntrst Unit dbgu_rxd ...
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Reset Controller • Based on one power-on reset cell and a double brownout detector • Status of the last reset, either Power-up Reset, Software Reset, User Reset, Watchdog Reset, Brownout Reset • Controls the internal resets and the NRST ...
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Main Oscillator frequency ranges between 3 and 20 MHz • Main Oscillator can be bypassed • PLL output ranges between 80 and 220 MHz It provides SLCK, MAINCK and PLLCK. Figure 9-2. 9.3 Power Management Controller The Power Management ...
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Figure 9-3. 9.4 Advanced Interrupt Controller • Controls the interrupt lines (nIRQ and nFIQ ARM Processor • Individually maskable and vectored interrupt sources – Source 0 is reserved for the Fast Interrupt Input (FIQ) – Source 1 is ...
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Debug Unit • Comprises: – One two-pin UART – One Interface for the Debug Communication Channel (DCC) support – One set of Chip ID Registers – One Interface providing ICE Access Prevention • Two-pin UART – USART-compatible User Interface ...
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Synchronous output, provides Set and Clear of several I/O lines in a single write 9.10 Voltage Regulator Controller The purpose of this controller is to select the Power Mode of the Voltage Regulator between Normal Mode (bit 0 is ...
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Peripherals 10.1 User Interface The User Peripherals are mapped in the 256 MBytes of the address space between 0xF000 0000 and 0xFFFF EFFF. Each peripheral is allocated 16 Kbytes of address space. A complete memory map is presented in ...
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Peripheral Multiplexing on PIO Lines The SAM7SE512/256/32 features three PIO controllers, PIOA, PIOB and PIOC, that multiplex the I/O lines of the peripheral set. PIO Controller A and B control 32 lines; PIO Controller C controls 24 lines. Each ...
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PIO Controller A Multiplexing Table 10-2. Multiplexing on PIO Controller A PIO Controller A I/O Line Peripheral A PA0 PWM0 PA1 PWM1 PA2 PWM2 PA3 TWD PA4 TWCK PA5 RXD0 PA6 TXD0 PA7 RTS0 PA8 CTS0 PA9 DRXD PA10 ...
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PIO Controller B Multiplexing Table 10-3. Multiplexing on PIO Controller B PIO Controller B I/O Line Peripheral A PB0 TIOA0 PB1 TIOB0 PB2 SCK0 PB3 NPCS3 PB4 TCLK0 PB5 NPCS3 PB6 PCK0 PB7 PWM3 PB8 ADTRG PB9 NPCS1 PB10 ...
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PIO Controller C Multiplexing Multiplexing on PIO Controller C PIO Controller C I/O Line Peripheral A PC0 D0 PC1 D1 PC2 D2 PC3 D3 PC4 D4 PC5 D5 PC6 D6 PC7 D7 PC8 D8 PC9 D9 PC10 D10 PC11 ...
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Programmable phase and polarity per chip select – Programmable transfer delays per chip select, between consecutive transfers and – Programmable delay between consecutive transfers – Selectable mode fault detection ...
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Offers a configurable frame sync and data length • Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal • Receiver and transmitter include a data signal, a clock ...
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USB Device Port • USB V2.0 full-speed compliant,12 Mbits per second. • Embedded USB V2.0 full-speed transceiver • Embedded 2688-byte dual-port RAM for endpoints • Eight endpoints – Endpoint 0: 64bytes – Endpoint 1 and 2: 64 bytes ping-pong ...
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ARM7TDMI Processor Overview 11.1 Overview The ARM7TDMI core executes both the 32-bit ARM and 16-bit Thumb instruction sets, allowing the user to trade off between high performance and high code density.The ARM7TDMI proces- sor implements Von Neuman architecture, using ...
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ARM7TDMI Processor For further details on ARM7TDMI, refer to the following ARM documents: ARM Architecture Reference Manual (DDI 0100E) ARM7TDMI Technical Reference Manual (DDI 0210B) 11.2.1 Instruction Type Instructions are either 32 bits long (in ARM state ...
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Table 11-1. User and System Mode R10 R11 R12 R13 R14 PC CPSR Registers are unbanked registers. This means that each of them refers to the same ...
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A seventh processing mode, System Mode, does not have any banked registers. It uses the User Mode registers. System Mode runs tasks that require a privileged processor mode and allows them to invoke all classes of exceptions. 11.2.4.2 Status Registers ...
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Table 11-2 Table 11-2. Mnemonic MOV ADD SUB RSB CMP TST AND EOR MUL SMULL SMLAL MSR B BX LDR LDRSH LDRSB LDRH LDRB LDRBT LDRT LDM SWP MCR LDC 11.2.6 Thumb Instruction Set Overview The Thumb instruction set is ...
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Program Counter (ARM Register 15), the Link Register (ARM Register 14) and the Stack Pointer (ARM Register 13). Further instructions allow limited access to the ARM registers 8 to 15. Table 11-3 Table 11-3. Mnemonic MOV ADD ...
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Debug and Test Features 12.1 Overview The SAM7SE Series Microcontrollers feature a number of complementary debug and test capa- bilities. A common JTAG/ICE (Embedded ICE) port is used for standard debugging functions, such as downloading code and single-stepping through ...
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Application Examples 12.3.1 Debug Environment Figure 12-2 standard debugging functions, such as downloading code and single-stepping through the program. Figure 12-2. Application Debug Environment Example SAM7SE512/256/32 Preliminary 50 shows a complete debug environment example. The ICE/JTAG interface is used ...
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Test Environment Figure 12-3 ter. In this example, the “board in test” is designed using a number of JTAG-compliant devices. These devices can be connected to form a single scan chain. Figure 12-3. Application Test Environment Example 12.4 Debug ...
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Functional Description 12.5.1 Test Pin One dedicated pin, TST, is used to define the device operating mode. The user must make sure that this pin is tied at low level to ensure normal operating conditions. Other values associated with ...
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IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS functions are implemented. In ICE debug mode, the ARM processor responds with a non-JTAG chip ID that identifies the processor to the ICE system. ...
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ID Code Register Access: Read-only 31 30 VERSION PART NUMBER 7 6 • VERSION[31:28]: Product Version Number Set to 0x0. • PART NUMBER[27:12]: Product Part Number Chip Name AT91SAM7SE32 AT91SAM7SE256 AT91SAM7SE512 • MANUFACTURER IDENTITY[11:1] Set ...
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Reset Controller (RSTC) The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the sys- tem without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the ...
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Functional Description 13.2.1 Reset Controller Overview The Reset Controller is made NRST Manager, a Brownout Manager, a Startup Counter and a Reset State Manager. It runs at Slow Clock and generates the following reset signals: • ...
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The Reset Controller can also be programmed to generate an interrupt instead of generating a reset so, the bit URSTIEN in RSTC_MR must be written at 1. 13.2.2.2 NRST External Reset Control The Reset State Manager asserts the ...
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Power-up Reset When VDDCORE is powered on, the Main Supply POR cell output is filtered with a start-up counter that operates at Slow Clock. The purpose of this counter is to ensure that the Slow Clock oscillator is stable ...
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Figure 13-5. User Reset State SLCK Any MCK Freq. NRST Resynch. 2 cycles proc_nreset RSTTYP Any periph_nreset NRST (nrst_out) 13.2.4.3 Brownout Reset When the brown_out/bod_reset signal is asserted, the Reset State Manager immediately enters the Brownout Reset. In this state, ...
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Figure 13-6. Brownout Reset State SLCK Any MCK Freq. brown_out or bod_reset proc_nreset RSTTYP Any periph_nreset NRST (nrst_out) 13.2.4.4 Software Reset The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing ...
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As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the Status Register (RSTC_SR cleared as soon as the software reset is left. No other software reset can be ...
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Figure 13-8. Watchdog Reset Only if WDRPROC = 0 13.2.5 Reset State Priorities The Reset State Manager manages the following priorities between the different reset sources, given in descending order: • Power-up Reset • Brownout Reset • Watchdog Reset • ...
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RSTTYP field: This field gives the type of the last reset, as explained in previous sections. • SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be performed ...
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Reset Controller Control Register Name: RSTC_CR Access: Write-only – – – – – – • PROCRST: Processor Reset effect KEY is correct, resets the processor. ...
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Reset Controller Status Register Name: RSTC_SR Access: Read-only 31 30 – – – – – – – – • URSTS: User Reset Status high-to-low edge on NRST happened since the ...
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Access: Read/Write – – – – – – • URSTEN: User Reset Enable 0 = The detection of a low level on the pin NRST does not generate a User Reset. 1 ...
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Real-time Timer (RTT) 14.1 Overview The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It gen- erates a periodic interrupt or/and triggers an alarm on a programmed value. 14.2 Block Diagram Figure 14-1. ...
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The Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (Real-time Value Register). As this value can be updated asynchronously from the Master Clock advis- able to read this register twice at the ...
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Real-time Timer (RTT) User Interface Table 14-1. Real-time Timer (RTT) Register Mapping Offset Register 0x00 Mode Register 0x04 Alarm Register 0x08 Value Register 0x0C Status Register 6222F–ATARM–14-Jan-11 SAM7SE512/256/32 Preliminary Name Access RTT_MR Read/Write RTT_AR Read/Write RTT_VR Read-only RTT_SR Read-only ...
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Real-time Timer Mode Register Name: RTT_MR Access: Read/Write 31 30 – – – – • RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the real-time timer. RTPRES ...
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Real-time Timer Alarm Register Name: RTT_AR Access: Read/Write • ALMV: Alarm Value Defines the alarm value (ALMV+1) compared with the Real-time Timer. 14.4.3 Real-time Timer Value Register Name: RTT_VR Access: Read-only ...
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Real-time Timer Status Register Name: RTT_SR Access: Read-only 31 30 – – – – – – – – • ALMS: Real-time Alarm Status 0 = The Real-time Alarm has not occurred since the ...
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Watchdog Timer (WDT) 15.1 Overview The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period seconds ...
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Functional Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock supplied with VDDCORE. It restarts with initial values on processor reset. The Watchdog is built around a ...
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Figure 15-2. Watchdog Behavior FFF Normal behavior WDV Forbidden Window WDD Permitted Window 0 Watchdog Fault 6222F–ATARM–14-Jan-11 SAM7SE512/256/32 Preliminary Watchdog Error WDT_CR = WDRSTT Watchdog Underflow if WDRSTEN WDRSTEN ...
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Watchdog Timer (WDT) User Interface Table 15-1. Watchdog Timer (WDT) Register Mapping Offset Register 0x00 Control Register 0x04 Mode Register 0x08 Status Register 15.4.1 Watchdog Timer Control Register Name: WDT_CR Access: Write-only – – 15 ...
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Watchdog Timer Mode Register Name: WDT_MR Access: Read/Write Once 31 30 – – WDIDLEHLT WDDIS WDRPROC WDRSTEN 7 6 • WDV: Watchdog Counter Value Defines the value loaded in the 12-bit Watchdog Counter. • WDFIEN: ...
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WDDIS: Watchdog Disable 0: Enables the Watchdog Timer. 1: Disables the Watchdog Timer. 15.4.3 Watchdog Timer Status Register Name: WDT_SR Access: Read-only 31 30 – – – – – – – – • ...
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Periodic Interval Timer (PIT) 16.1 Overview The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt designed to offer maximum accuracy and efficient management, even for systems with long response time. 16.2 Block Diagram Figure 16-1. ...
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Functional Description The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems. The PIT provides a programmable overflow counter and a reset-on-read feature built around two counters: a 20-bit CPIV counter and a ...
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Figure 16-2. Enabling/Disabling PIT with PITEN 15 MCK Prescaler 0 PITEN CPIV 0 PICNT PITS (PIT_SR) APB Interface 6222F–ATARM–14-Jan-11 SAM7SE512/256/32 Preliminary MCK 1 PIV - 1 PIV 1 0 read PIT_PIVR APB cycle APB cycle restarts MCK Prescaler 0 0 ...
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Periodic Interval Timer (PIT) User Interface Table 16-1. Periodic Interval Timer (PIT) Register Mapping Offset Register 0x00 Mode Register 0x04 Status Register 0x08 Periodic Interval Value Register 0x0C Periodic Interval Image Register SAM7SE512/256/32 Preliminary 82 Name Access PIT_MR Read/Write ...
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Periodic Interval Timer Mode Register Name: PIT_MR Access: Read/Write 31 30 – – – – • PIV: Periodic Interval Value Defines the value compared with the primary 20-bit counter of the Periodic Interval ...
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Periodic Interval Timer Value Register Name: PIT_PIVR Access: Read-only PICNT Reading this register clears PITS in PIT_SR. • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval ...
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Voltage Regulator Mode Controller (VREG) 17.1 Overview The Voltage Regulator Mode Controller contains one Read/Write register, the Voltage Regulator Mode Register. Its offset is 0x60 with respect to the System Controller offset. This register controls the Voltage Regulator Mode. ...
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Voltage Regulator Power Controller (VREG) User Interface Table 17-1. Voltage Regulator Power Controller Register Mapping Offset Register 0x60 Voltage Regulator Mode Register 17.2.1 Voltage Regulator Mode Register Name: VREG_MR Access: Read/Write 31 30 – – – – ...
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Memory Controller (MC) 18.1 Overview The Memory Controller (MC) manages the ASB bus and controls accesses requested by the masters, typically the ARM7TDMI processor and the Peripheral DMA Controller. It features a simple bus arbiter, an address decoder, an ...
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Functional Description The Memory Controller handles the internal ASB bus and arbitrates the accesses of both masters made up of: • A bus arbiter • An address decoder • An abort status • A misalignment detector • ...
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External Memory Areas Figure 18-2 Figure 18-2. External Memory Areas 18.4.1 Internal Memory Mapping Within the Internal Memory address space, the Address Decoder of the Memory Controller decodes eight more address bits to allocate 1-Mbyte address spaces for the ...
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Figure 18-3. Internal Memory Mapping 18.4.2 Internal Memory Area 0 The first 32 bytes of Internal Memory Area 0 contain the ARM processor exception vectors, in particular, the Reset Vector at address 0x0. Before execution of the remap command, the ...
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Abort Status There are three reasons for an abort to occur: • access to an undefined address • access to a protected area without the permitted state • an access to a misaligned address. When an abort occurs, a ...
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There is no priority in the protection of the memory spaces. In case of overlap between several memory spaces, the strongest protection is taken into account access is performed to an address which is not contained in any ...
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Memory Controller (MC) User Interface Base Address: 0xFFFFFF00 Table 18-1. Memory Controller (MC) Memory Mapping Offset Register 0x00 MC Remap Control Register 0x04 MC Abort Status Register 0x08 MC Abort Address Status Register 0x0C Reserved 0x10 MC Protection Unit ...
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MC Remap Control Register Name: MC_RCR Access: Write-only Absolute Address: 0xFFFF FF00 31 30 – – – – – – – – • RCB: Remap Command Bit 0: No effect. 1: This Command ...
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MC Abort Status Register Name: MC_ASR Access: Read-only Reset Value: 0x0 Absolute Address: 0xFFFF FF04 31 30 – – – – – – – – • UNDADD: Undefined Address Abort Status 0: The ...
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MST0: PDC Abort Source 0: The last aborted access was not due to the PDC. 1: The last aborted access was due to the PDC. • MST1: ARM7TDMI Abort Source 0: The last aborted access was not due to ...
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MC Abort Address Status Register Name: MC_AASR Access: Read-only Reset Value: 0x0 Absolute Address: 0xFFFF FF08 • ABTADD: Abort Address This field contains the address of the last aborted access. 6222F–ATARM–14-Jan-11 ...
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MC Protection Unit Area Registers Name: MC_PUIA0 - MC_PUIA15 Access: Read/Write Reset Value: 0x0 Absolute Address: 0xFFFFFF10 - 0xFFFFFF4C 31 30 – – – – SIZE • PROT: Protection PROT ...
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MC Protection Unit Peripheral Name: MC_PUP Access: Read/Write Reset Value: 0x000000000 Absolute Address: 0xFFFFFF50 31 30 – – – – – – – – • PROT: Protection PROT 0 0 Read/Write 0 1 ...
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MC Protection Unit Enable Register Name: MC_PUER Access: Read/Write Reset Value: 0x000000000 Absolute Address: 0xFFFFFF54 31 30 – – – – – – – – • PUEB: Protection Unit Enable Bit 0: The ...
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Embedded Flash Controller (EFC) 19.1 Overview The Embedded Flash Controller (EFC ) is a part of the Memory Controller and ensures the inter- face of the Flash block with the 32-bit internal bus. It increases performance in Thumb Mode ...
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Figure 19-1. Embedded Flash Memory Mapping 19.2.2 Read Operations An optimized controller manages embedded Flash reads. A system 32-bit buffers is added in order to start access at following address during the second read, thus increasing perfor- ...
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Figure 19-2. Code Read Optimization in Thumb Mode for FWS = 0 Master Clock ARM Request (16-bit) Code Fetch @Byte 0 @Byte 2 Flash Access Bytes 0-3 Buffer (32 bits) Data To ARM Bytes 0-1 When FWS is equal to ...
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Figure 19-4. Code Read Optimization in Thumb Mode for FWS = 3 3 Wait State Cycles Master Clock ARM Request (16-bit) Code Fetch @Byte 0 Flash Access Bytes 0-3 Buffer (32 bits) Data To ARM Note: When FWS is equal ...
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To run one of these commands, the field FCMD of the MC_FCR register has to be written with the command number. As soon as the MC_FCR register is written, the FRDY flag is automati- cally cleared. Once the current command ...
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Figure 19-5. Command State Chart In order to guarantee valid operations on the Flash memory, the field Flash Microsecond Cycle Number (FMCN) in the Flash Mode Register MC_FMR must be correctly programmed (see Flash Mode Register” on page 19.2.4.1 Flash ...
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Figure 19-6. Example of Partial Page Programming: 32 bits wide ... 16 words ... 16 words ...
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Erase All operation is allowed only if there are no lock bits set. Thus least one lock region is locked, the bit LOCKE in MC_FSR rises and the command is cancelled. If the bit LOCKE has been written ...
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General-purpose NVM Bits General-purpose NVM bits do not interfere with the embedded Flash memory plane. (Does not apply to EFC1 on the SAM7SE512.) These general-purpose bits are dedicated to protect other parts of the product. They can be set ...
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When the locking completes, the bit FRDY in the Flash Programming Status Register (MC_FSR) rises interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated. When the ...
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MC Flash Mode Register Name: MC_FMR Access: Read/Write Offset: (EFC0) 0x60 Offset: (EFC1) 0x70 31 30 – – – – NEBP – • FRDY: Flash Ready Interrupt Enable 0: Flash Ready does not ...
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FMCN: Flash Microsecond Cycle Number Before writing Non Volatile Memory bits (Lock bits, General Purpose NVM bit and Security bits), this field must be set to the number of Master Clock cycles in one microsecond. When writing the rest ...
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MC Flash Command Register Name: MC_FCR Access: Write-only Offset: (EFC0) 0x64 Offset: (EFC1) 0x74 – – – – • FCMD: Flash Command This field defines the Flash commands: FCMD 0000 0001 ...
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PAGEN: Page Number Command Write Page Command Write Page and Lock Command Erase All Command Set/Clear Lock Bit Command Set/Clear General Purpose NVM Bit Command Set Security Bit Command Note: Depending on the command, all the possible unused bits ...
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MC Flash Status Register Name: MC_FSR Access: Read-only Offset: (EFC0) 0x68 Offset: (EFC1) 0x78 31 30 LOCKS15 LOCKS14 23 22 LOCKS7 LOCKS6 15 14 – – – – • FRDY: Flash Ready Status 0: The EFC is ...
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SAM7SE512/256/32 Preliminary 116 6222F–ATARM–14-Jan-11 ...
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Fast Flash Programming Interface (FFPI) 20.1 Overview The Fast Flash Programming Interface provides two solutions - parallel or serial - for high-vol- ume programming using a standard gang programmer. The parallel interface is fully handshaked and the device is ...
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Parallel Fast Flash Programming 20.2.1 Device Configuration In Fast Flash Programming Mode, the device specific test mode. Only a certain set of pins is significant. Other pins must be left unconnected. Figure 20-1. Parallel Programming Interface ...
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Table 20-1. Signal Description List (Continued) Signal Name Function PGMNCMD Valid command available 0: Device is busy PGMRDY 1: Device is ready for a new command PGMNOE Output Enable (active high) 0: DATA[15: input mode PGMNVALID 1: DATA[15:0] ...
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When MODE is equal to CMDE, then a new command (strobed on DATA[15:0] signals) is stored in the command register. Table 20-3. DATA[15:0] 0x0011 0x0012 0x0022 0x0032 0x0042 0x0013 0x0014 0x0024 0x0015 0x0034 0x0044 0x0025 0x0054 0x0035 0x001F 0x0016 0x001E ...
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Write Handshaking For details on the write handshaking sequence, refer to Figure 20-2. Parallel Programming Timing, Write Sequence Table 20-4. Write Handshake Step Programmer Action 1 Sets MODE and DATA signals 2 Clears NCMD signal 3 Waits for RDY ...
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Read Handshaking For details on the read handshaking sequence, refer to Figure 20-3. Table 20-5. Read Handshake Step Programmer Action 1 Sets MODE and DATA signals 2 Clears NCMD signal 3 Waits for RDY low 4 Sets DATA signal ...
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Device Operations Several commands on the Flash memory are available. These commands are summarized in Table 20-3 on page face running several read/write handshaking sequences. When a new command is executed, the previous one is automatically achieved. Thus, chaining ...
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The Write Page command (WP) is optimized for consecutive writes. Write handshaking can be chained; an internal address buffer is automatically increased. Table 20-7. Step ... n n+1 n+2 n+3 n+4 n+5 ... ...
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Flash Lock Commands Lock bits can be set using WPL or EWPL commands. They can also be set by using the Set Lock command (SLB). With this command, several lock bits can be activated. A Bit Mask is pro- ...
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Flash Security Bit Command A security bit can be set using the Set Security Bit command (SSE). Once the security bit is active, the Fast Flash programming is disabled. No other command can be run. An event on the ...
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Table 20-15. Write Command (Continued) Step n+4 n+5 ... 20.2.5.9 Get Version Command The Get Version (GVE) command retrieves the version of the FFPI interface. Table 20-16. Get Version Command Step 1 2 6222F–ATARM–14-Jan-11 SAM7SE512/256/32 Preliminary Handshake Sequence MODE[3:0] Write ...
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Serial Fast Flash Programming The Serial Fast Flash programming interface is based on IEEE Std. 1149.1 “Standard Test Access Port and Boundary-Scan Architecture”. Refer to this standard for an explanation of terms used in this chapter and for a ...
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Table 20-17. Signal Description List (Continued) Signal Name Function TST Test Mode Select PGMEN0 Test Mode Select PGMEN1 Test Mode Select TCK JTAG TCK TDI JTAG Test Data In TDO JTAG Test Data Out TMS JTAG Test Mode Select 20.3.2 ...
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Read/Write Handshake The read/write handshake is done by carrying out read/write operations on two registers of the device that are accessible through the JTAG: • Debug Comms Control Register: DCCR • Debug Comms Data Register: DCDR Access to these ...
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Flash Read Command This command is used to read the Flash contents. The memory map is accessible through this command. Memory is seen as an array of words (32-bit wide). The read command can start at any valid address ...
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Flash Full Erase Command This command is used to erase the Flash memory planes. All lock bits must be deactivated before using the Full Erase command. This can be done by using the CLB command. Table 20-21. Full Erase ...
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GP NVM bits can be read using Get Fuse Bit command (GFB). When a bit set in the Bit Mask is returned, then the corresponding fuse bit is set. Table 20-25. Get General-purpose NVM Bit Command Read/Write Write Read 20.3.4.6 ...
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Get Version Command The Get Version (GVE) command retrieves the version of the FFPI interface. Table 20-29. Get Version Command Read/Write Write Read SAM7SE512/256/32 Preliminary 134 DR Data GVE Version 6222F–ATARM–14-Jan-11 ...
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External Bus Interface (EBI) 21.1 Overview The External Bus Interface (EBI) is designed to ensure the successful data transfer between several external devices and the embedded Memory Controller of an ARM-based device. The Static Memory, SDRAM and ECC Controllers ...
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Block Diagram Figure 21-1. Organization of the External Bus Interface Memory Controller ASB Address Decoder SAM7SE512/256/32 Preliminary 136 External Bus Interface SDRAM Controller MUX Logic Static Memory Controller CompactFlash Logic NAND Flash Logic ECC Controller Chip Select Assignor User ...
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I/O Lines Description Table 21-1. I/O Lines Description Name Function D[31:0] Data Bus A[22:0] Address Bus NWAIT External Wait Signal NCS[7:0] Chip Select Lines NWR[1:0] Write Signals NRD Read Signal NWE Write Enable NUB NUB: Upper Byte Select NLB ...
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The connection of some signals through the Mux logic is not direct and depends on the Memory Controller in use at the moment. Table 21-2 Table 21-2. EBI Pins NWR1/NBS1/CFIOR A0/NBS0 A1/NBS2 A[11:2] SDA10 A12 A[14:13] A[22:15] D[31:16] D[15:0] 21.4 ...
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Table 21-3. EBI Pins and External Static Device Connections (Continued) 8-bit Static Device Pin Controller A18 - A20 A18 - A20 A21/NANDALE A21 A22/REG/NANDCLE A22 NCS0 CS NCS1/SDCS CS NCS2/CFCS1 CS NCS3/NANDCS CS NCS4/CFCS0 CS NCS5/CFCE1 CS NCS6/CFCE2 CS NCS7 ...
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When the NAND Flash Logic is used, NWR0/NWE/CFWE must be kept as PIO Input Mode with Pull-up enabled (default state after reset PIO Output set at logic level 1. The PIO cannot be used in PIO Mode. ...
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Product Dependencies 21.5.1 I/O Lines The pins used for interfacing the External Bus Interface may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the External Bus Interface pins to their peripheral ...
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NCS4 and/or NCS2 (i.e., between 0x5000 0000 and 0x5FFF FFFF for NCS4 and between 0x3000 0000 and 0x3FFF FFFF for NCS2). When multiplexed with CFCE1 and CFCE2 signals, the NCS5 and NCS6 signals become unavailable. Performing ...
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Table 21-4. CFCE1 and CFCE2 Truth Table Mode CFCE2 Attribute Memory NUB NUB Common Memory 1 NUB I/O Mode 1 Task File 1 Data Register 1 Control Register 0 Alternate Status Read Drive Address 0 Standby Mode or Address Space ...
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Figure 21-4. CompactFlash Read/Write Control Signals Table 21-5. CompactFlash Mode Selection Mode Base Address CFOE Attribute Memory Common Memory I/O Mode True IDE Mode 21.6.5.4 Multiplexing of CompactFlash Signals on EBI Pins Table 21-6 nals with other EBI signals on ...
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Table 21-7. Shared CompactFlash Interface Multiplexing Pins NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NBS3/CFIOW NCS0/CFRNW 21.6.5.5 Application Example Figure 21-5 on page 145 CFRNW signals are not directly connected to the CompactFlash slot 0, but do control the direc- tion and the output ...
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NAND Flash Support The EBI integrates circuitry that interfaces to NAND Flash devices. The NAND Flash logic is driven by the Static Memory Controller on the NCS3 address space. Programming the CS3A field in the Chip Select Assignment Register ...
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Figure 21-7. NAND Flash Application Example Note: 6222F–ATARM–14-Jan-11 SAM7SE512/256/32 Preliminary D[7:0] A22/REG/NANDCLE A21/NANDALE NCS3/NANDCS EBI NANDOE NANDWE PIO PIO The External Bus Interface is also able to support 16-bit devices. AD[7:0] CLE ALE Not Connected NAND Flash NOE NWE CE ...
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Implementation Examples 21.7.1 16-bit SDRAM 21.7.1.1 Hardware Configuration D[0..15] A[0..14] (Not used A12) 21.7.1.2 Software Configuration The following configuration must be respected: • Address lines A[0..11], A[13-14], BA0, BA1, SDA10, SDCS_NCS1, SDWE, SDCKE, NBS1, RAS, CAS, and data lines ...
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SDRAM 21.7.2.1 Hardware Configuration D[0..31] A[0..14] (Not used A12 A10 A11 SDA10 SDA10 A13 BA0 BA0 BA1 BA1 A14 SDCKE SDCKE SDCK SDCK 1%6 A0 1%6 CFIOR_NBS1_NWR1 CAS CAS RAS ...
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NAND Flash 21.7.3.1 Hardware Configuration D[0..7] CLE ALE NANDOE NANDWE (ANY PIO) (ANY PIO) 21.7.3.2 Software Configuration The following configuration must be respected: • CLE, ALE, NANDOE and NANDWE signals are multiplexed with PIO lines and thus the ...
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NAND Flash 21.7.4.1 Hardware Configuration D[0..15] CLE ALE NANDOE NANDWE (ANY PIO) (ANY PIO) 21.7.4.2 Software Configuration The software configuration is the same as for an 8-bit NAND Flash except the data bus width programmed in the mode ...
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NOR Flash on NCS0 21.7.5.1 Hardware Configuration D[0..15] A[1..22] NRST NWE NCS0 NRD 21.7.5.2 Software Configuration • Address lines A[1..22], NCS0, NRD, NWE and data lines D[8..15] are multiplexed with PIO lines and thus dedicated PIOs must be programmed ...
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CompactFlash 21.7.6.1 Hardware Configuration D[0..15] D15 D14 D13 D12 D11 D10 CFRNW 4 CFCSx (CFCS0 or CFCS1) 5 (ANY PIO) CARD DETEC T A[0..10] A10 ...
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Software Configuration The following configuration must be respected: • Assign the EBI CS4 and/or EBI_CS5 to the CompactFlash Slot 0 and/or Slot 1 by setting the bit EBI_CS4A and/or EBI_CS5A in the EBI Chip Select Assignment Register. • Select ...
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CompactFlash True IDE 21.7.7.1 Hardware Configuration D[0..15] D15 D14 D13 D12 D11 D10 CFRNW 4 CFCSx (CFCS0 or CFCS1) 5 (ANY PIO) CARD DETECT A[0..10] A10 ...
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Software Configuration The following configuration must be respected: • Address lines A[0..10], A22, CFWE, CFOE, CFIOW, CFIOR, NWAIT, CFRNW, CFS0, CFCS1, CFCE1, CFCE2 and data lines D[8..15] are multiplexed with PIO lines and thus the dedicated PIOs must be ...
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External Bus Interface (EBI) User Interface EBI User Interface Base Address: 0xFFFF FF80 Table 21-8. External Bus Interface Memory Map Offset Register 0x00 Chip Select Assignment Register 0x04 Reserved 0x08 Reserved 0x0C Reserved 0x10 - 0x2C SMC User Interface ...
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EBI Chip Select Assignment Register Name: EBI_CSA Access: Read/Write Reset Value: 0x0 Offset: 0x0 Absolute Address: 0xFFFF FF80 31 30 – – – – – – – – • CS1A: Chip Select 1 ...
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SAM7SE512/256/32 Preliminary 159 ...
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SAM7SE512/256/32 Preliminary 160 6222F–ATARM–14-Jan-11 ...
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Static Memory Controller (SMC) 22.1 Overview The Static Memory Controller (SMC) generates the signals that control the access to external static memory or peripheral devices. The SMC is fully programmable. It has eight chip selects and a 23-bit address ...
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I/O Lines Description Table 22-1. I/O Lines Description Name Description NCS[7:0] Static Memory Controller Chip Select Lines NRD Read Signal NWR0/NWE Write 0/Write Enable Signal NWR1/NUB Write 1/Upper Byte Select Signal A0/NLB Address Bit 0/Lower Byte Select Signal A[22:1] ...
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Product Dependencies 22.5.1 I/O Lines The pins used for interfacing the Static Memory Controller may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the Static Memory Con- troller pins to their ...
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Chip Select Lines The Static Memory Controller provides up to eight chip select lines: NCS0 to NCS7. Figure 22-3. Memory Connections for Eight External Devices NCS[7:0] NRD SMC NWR[1:0] A[22:0] D[15:0] Note: 1. The maximum address space per device ...
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Figure 22-5. Memory Connection for a 16-bit Data Path Device 22.6.2 Write Access 22.6.2.1 Write Access Type Each chip select with a 16-bit data bus can operate with one of two different types of write access: • Byte Write Access ...
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Figure 22-6. Memory Connection for 2 x 8-bit Data Path Devices 22.6.2.3 Byte Select Access Byte Select Access is used to connect 16-bit devices in a memory page. • The signal A0/NLB is used as NLB and enables the lower ...
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Figure 22-8 on NCS2 (BAT = 1). Figure 22-8. Connection to a 16-bit Data Path Device without Byte Write Capability 22.6.2.4 Write Data Hold Time During write cycles, data output becomes valid after the rising edge of MCK and remains ...
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Figure 22-10. Write Access with 1 Wait State 22.6.3 Read Access 22.6.3.1 Read Protocols The SMC provides two alternative protocols for external memory read accesses: standard and early read. The difference between the two protocols lies in the behavior of ...
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Figure 22-11. Standard Read Protocol 22.6.3.3 Early Read Protocol Early read protocol provides more time for a read access from the memory by asserting NRD at the beginning of the clock cycle. In the case of successive read cycles in ...
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Standard Wait States Each chip select can be programmed to insert one or more wait states during an access on the corresponding memory area. This is done by setting the WSEN field in the corresponding SMC_CSR grammed in the ...
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Figure 22-14. NWAIT Behavior in Read Access [NWS = 3] MCK A[22:0] NWAIT NWAIT internally synchronized NRD NCS (1) Wait Delay from NRD Notes: 1. Early Read Protocol 2. Standard Read Protocol Figure 22-15. NWAIT Behavior in Write Access [NWS ...
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Data float wait states do not delay internal memory accesses. Hence, a single access to an external ...
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Figure 22-17. Chip Select Wait State Notes: 22.6.4.5 Early Read Wait State In early read protocol, an early read wait state is automatically inserted when an external write cycle is followed by a read cycle to allow time for the ...
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Setup and Hold Cycles The SMC allows some memory devices to be interfaced with different setup, hold and pulse delays. These parameters are programmable and define the timing of each portion of the read and write cycles. However, it ...
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Write Access The write cycle can be divided into a setup, a pulse length and a hold. The setup parameter can have a value between 1.5 and 7.5 clock cycles, the hold parameter between 0.5 and 7 clock cycles ...
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Data Float Wait States with Setup Cycles Figure 22-23. Consecutive Accesses with Setup Programmed on the Second Access MCK A[22:0] NCS1 NCS2 NWE NRD Figure 22-24. First Access with Data Float Wait States (TDF = 2) and Second Access ...
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Figure 22-25. First Access with Data Float Wait States (TDF = 2) and Second Access with Setup (NRDSETUP = 3) MCK A[22:0] NCS1 NCS2 NRD D[15:0] 6222F–ATARM–14-Jan-11 SAM7SE512/256/32 Preliminary Setup Data Float Time 177 ...
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LCD Interface Mode The SMC can be configured to work with an external liquid crystal display (LCD) controller by setting the ACSS (Address to Chip Select Setup) bit in the SMC_CSR registers Select Registers” on page In LCD mode, ...
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Memory Access Waveforms 22.6.7.1 Read Accesses in Standard and Early Protocols Figure 22-28 on page 179 for external memory read protocol. Figure 22-28. Standard Read Protocol without t Read Mem 1 MCK A[22:0] NRD NWE NCS1 NCS2 D[15:0] (Mem ...
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Figure 22-29. Early Read Protocol without t Read Mem 1 MCK A[22:0] NRD NWE NCS1 NCS2 D[15:0] (Mem 1) D[15:0] (to write) D[15:0] (Mem 2) SAM7SE512/256/32 Preliminary 180 DF Write Early Read Read Mem 1 Wait Cycle Mem 1 Mem ...
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Figure 22-30. Standard Read Protocol with t Mem 1 Read Mem 1 Data Float Wait MCK A[22:0] NRD NWE NCS1 NCS2 D[15:0] (Mem 1) D[15:0] (to write) D[15:0] (Mem 2) 6222F–ATARM–14-Jan-11 SAM7SE512/256/32 Preliminary ...
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Figure 22-31. Early Read Protocol with t Write Mem 1 Read Mem 1 Data Float Wait MCK A[22:0] NRD NWE NCS1 NCS2 t DF D[15:0] (Mem 1) D[15:0] (to write) D[15:0] (Mem 2) SAM7SE512/256/32 Preliminary 182 DF Early Read Read ...
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Accesses with Setup and Hold Figure 22-32 Hold Cycles. Figure 22-32. Read Accesses in Standard Read Protocol with Setup and Hold MCK A[22:1] 00d2b A0/NLB NRD NWR0/NWE NWR1/NUB Setup NCS D[15:0] e59f Note: 1. Read access, memory data bus ...
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Accesses Using NWAIT Input Signal Figure 22-34 on page 184 NWAIT. Figure 22-34. Write Access using NWAIT in Byte Select Type Access Chip Select Wait MCK NWAIT NWAIT internally synchronized A[22:1] 000008A NRD NWR0/NWE A0/NLB NWR1/NUB NCS D[15:0] 1312 ...
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Figure 22-35. Write Access using NWAIT in Byte Write Type Access Chip Select Wait MCK NWAIT NWAIT internally synchronized 000008C A[22:1] A0/NLB NRD NWR0/NWE NWR1/NUB NCS D[15:0] Wait Delay Falling from NWR0/NWE/NWR1/NUB Note: 1. Write access memory, data bus width ...
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Figure 22-36. Write Access using NWAIT Chip Select Wait MCK NWAIT NWAIT internally synchronized 0000033 A[22:1] A0/NLB NRD NWR0/NWE NWR1/NUB NCS D[15:0] Wait Delay Falling from NWR0/NWE Note: 1. Write access memory, data bus width = 8 bits, WSEN = ...
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Figure 22-37. Read Access in Standard Protocol using NWAIT MCK NWAIT NWAIT internally synchronized 0002C44 A[22:1] A0/NLB NRD NWR0/NWE NWR1/NUB NCS D[15:0] Wait Delay Falling from NRD/NOE Note: 1. Read access, memory data bus width = 16, NWS = 5, ...
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Figure 22-38. 0 Wait State, 16-bit Bus Width, Word Transfer MCK A[22:1] NCS NLB NUB Read Access · Standard Read Protocol NRD D[15:0] · Early Read Protocol NRD D[15:0] Write Access · Byte Write/ Byte Select Option NWE D[15:0] SAM7SE512/256/32 ...
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Figure 22-39. 1 Wait State, 16-bit Bus Width, Word Transfer MCK A[22:1] NCS NLB NUB Read Access · Standard Read Protocol NRD D[15:0] · Early Read Protocol NRD D[15:0] Write Access · Byte Write/ Byte Select Option NWE D[15:0] 6222F–ATARM–14-Jan-11 ...
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Figure 22-40. 1 Wait State, 16-bit Bus Width, Half-Word Transfer MCK A[22:1] NCS NLB NUB Read Access · Standard Read Protocol NRD D[15:0] · Early Read Protocol NRD D[15:0] Write Access · Byte Write/ Byte Select Option NWE D[15:0] SAM7SE512/256/32 ...
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Figure 22-41. 0 Wait State, 8-bit Bus Width, Word Transfer MCK addr A[22:0] NCS Read Access · Standard Read Protocol NRD D[15:0] · Early Read Protocol NRD D[15:0] Write Access NWR0 NWR1 D[15:0] 6222F–ATARM–14-Jan-11 SAM7SE512/256/32 Preliminary addr+1 addr ...
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Figure 22-42. 1 Wait State, 8-bit Bus Width, Half-Word Transfer 1 Wait State MCK A[22:0] NCS Read Access · Standard Read, Protocol NRD D[15:0] · Early Read Protocol NRD D[15:0] Write Access NWR0 NWR1 D[15:0] SAM7SE512/256/32 Preliminary 192 1 Wait ...
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Figure 22-43. 1 Wait State, 8-bit Bus Width, Byte Transfer MCK A[22:0] NCS Read Access · Standard Read Protocol NRD D[15:0] · Early Read Protocol NRD D[15:0] Write Access NWR0 NWR1 D[15:0] 6222F–ATARM–14-Jan-11 SAM7SE512/256/32 Preliminary 1 Wait State X B ...
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Figure 22-44. 0 Wait State, 16-bit Bus Width, Byte Transfer MCK A[22:1] Internal Address Bus NCS NLB NUB Read Access · Standard Read Protocol NRD D[15:0] · Early Read Protocol NRD D[15:0] Write Access · Byte Write Option NWR0 NWR1 ...
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Static Memory Controller (SMC) User Interface The Static Memory Controller is programmed using the registers listed in (SMC_CSR0 to SMC_CSR7) are used to program the parameters for the individual external memories. Table 22-4. Static Memory Controller Register Mapping Offset ...
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SMC Chip Select Registers Name: SMC_CSR0..SMC_CSR7 Access: Read/Write Reset Value: See Table 22-4 on page 195 31 30 – RWHOLD 23 22 – – DRP DBW 7 6 WSEN • NWS: Number of Wait States This field ...
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DBW: Data Bus Width DBW • DRP: Data Read Protocol 0: Standard Read Protocol is used. 1: Early Read Protocol is used. • ACSS: Address to Chip Select Setup ACSS • ...
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Figure 22-45. Read/Write Setup Figure 22-46. Read Hold Figure 22-47. Write Hold SAM7SE512/256/32 Preliminary 198 MCK A[22:0] NRD NWE RWSETUP MCK A[22:0] NRD RWHOLD MCK A[22:0] NWE D[15:0] RWHOLD 6222F–ATARM–14-Jan-11 ...
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SDRAM Controller (SDRAMC) 23.1 Overview The SDRAM Controller (SDRAMC) extends the memory capabilities of a chip by providing the interface to an external 16-bit or 32-bit SDRAM device. The page size supports ranges from 2048 to 8192 and the ...
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I/O Lines Description Table 23-1. I/O Line Description Name Description SDCK SDRAM Clock SDCKE SDRAM Clock Enable SDCS SDRAM Controller Chip Select BA[1:0] Bank Select Signals RAS Row Signal CAS Column Signal SDWE SDRAM Write Enable NBS[3:0] Data Mask ...