AT91SAM7SE256B-CUR Atmel, AT91SAM7SE256B-CUR Datasheet - Page 376

• Manufacturer Part Number: AT91SAM7SE256B-CUR
• Description: IC ARM7 MCU FLASH 256K 128-LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7SE256B-CUR

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: EBI/EMI, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 88
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: SAM7SE256
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 88
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Processor To Be Evaluated: AT91SAM7SE256B
• Supply Current (max): 60 uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

32.10.1
Name:
Access:
Reset Value: 0x00000000
• START: Send a START Condition
0 = No effect.
1 = A frame beginning with a START bit is transmitted according to the features defined in the mode register.
This action is necessary when the TWI peripheral wants to read data from a slave. When configured in Master Mode with a
write operation, a frame is sent as soon as the user writes a character in the Transmit Holding Register (TWI_THR).
• STOP: Send a STOP Condition
0 = No effect.
1 = STOP Condition is sent just after completing the current byte transmission in master read mode.
• MSEN: TWI Master Mode Enabled
0 = No effect.
1 = If MSDIS = 0, the master mode is enabled.
Note:
• MSDIS: TWI Master Mode Disabled
0 = No effect.
1 = The master mode is disabled, all pending data is transmitted. The shifter and holding characters (if it contains data) are
transmitted in case of write operation. In read operation, the character being transferred must be completely received
before disabling.
376
SWRST
– In single data byte master read, the START and STOP must both be set.
– In multiple data bytes master read, the STOP must be set after the last data received but one.
– In master read mode, if a NACK bit is received, the STOP is automatically performed.
– In multiple data write operation, when both THR and shift register are empty, a STOP condition is automatically
31
23
15
–
–
–
7
sent.
Switching from Slave to Master mode is only permitted when TXCOMP = 1.
SAM7SE512/256/32 Preliminary
TWI Control Register
TWI_CR
Write-only
30
22
14
–
–
–
6
–
SVDIS
29
21
13
–
–
–
5
SVEN
28
20
12
–
–
–
4
MSDIS
27
19
11
–
–
–
3
MSEN
26
18
10
–
–
–
2
STOP
25
17
–
–
9
–
1
6222F–ATARM–14-Jan-11
START
24
16
–
–
8
–
0