AT91SAM7SE256B-CUR Atmel, AT91SAM7SE256B-CUR Datasheet - Page 52

• Manufacturer Part Number: AT91SAM7SE256B-CUR
• Description: IC ARM7 MCU FLASH 256K 128-LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7SE256B-CUR

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: EBI/EMI, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 88
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: SAM7SE256
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 88
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Processor To Be Evaluated: AT91SAM7SE256B
• Supply Current (max): 60 uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

12.5
12.5.1
12.5.2
12.5.3
12.5.4
52
Functional Description
SAM7SE512/256/32 Preliminary
Test Pin
EmbeddedICE
Debug Unit
IEEE 1149.1 JTAG Boundary Scan
™
One dedicated pin, TST, is used to define the device operating mode. The user must make sure
that this pin is tied at low level to ensure normal operating conditions. Other values associated
with this pin are reserved for manufacturing test.
The ARM7TDMI EmbeddedICE is supported via the ICE/JTAG port.The internal state of the
ARM7TDMI is examined through an ICE/JTAG port.
The ARM7TDMI processor contains hardware extensions for advanced debugging features:
There are three scan chains inside the ARM7TDMI processor that support testing, debugging,
and programming of the Embedded ICE. The scan chains are controlled by the ICE/JTAG port.
Embedded ICE mode is selected when JTAGSEL is low. It is not possible to switch directly
between ICE and JTAG operations. A chip reset must be performed after JTAGSEL is changed.
For further details on the Embedded ICE, see the ARM7TDMI (Rev4) Technical Reference Man-
ual (DDI0210B).
The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several
debug and trace purposes and offers an ideal means for in-situ programming solutions and
debug monitor communication. Moreover, the association with two peripheral data controller
channels permits packet handling of these tasks with processor time reduced to a minimum.
The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals
that come from the ICE and that trace the activity of the Debug Communication Channel.The
Debug Unit allows blockage of access to the system through the ICE interface.
A specific register, the Debug Unit Chip ID Register, gives information about the product version
and its internal configuration.
Table 12-2.
For further details on the Debug Unit, see the Debug Unit section.
IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging
technology.
Chip Name
AT91SAM7SE32
AT91SAM7SE256
AT91SAM7SE512
(Embedded In-circuit Emulator)
• In halt mode, a store-multiple (STM) can be inserted into the instruction pipeline. This exports
• In monitor mode, the JTAG interface is used to transfer data between the debugger and a
the contents of the ARM7TDMI registers. This data can be serially shifted out without
affecting the rest of the system.
simple monitor program running on the ARM7TDMI processor.
AT91SAM7SExx Chip IDs
0x272A0A40
0x272A0940
0x27280340
Chip ID
6222F–ATARM–14-Jan-11