AT91SAM7SE256B-CUR Atmel, AT91SAM7SE256B-CUR Datasheet - Page 168
AT91SAM7SE256B-CUR
Manufacturer Part Number
AT91SAM7SE256B-CUR
Description
IC ARM7 MCU FLASH 256K 128-LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7SE256-AU.pdf
(673 pages)
Specifications of AT91SAM7SE256B-CUR
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
EBI/EMI, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
88
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
SAM7SE256
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SPI, USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
88
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 85 C
Processor To Be Evaluated
AT91SAM7SE256B
Supply Current (max)
60 uA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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22.6.3
22.6.3.1
22.6.3.2
168
SAM7SE512/256/32 Preliminary
Read Access
Read Protocols
Standard Read Protocol
Figure 22-10. Write Access with 1 Wait State
The SMC provides two alternative protocols for external memory read accesses: standard and
early read. The difference between the two protocols lies in the behavior of the NRD signal.
For write accesses, in both protocols, NWE has the same behavior. In the second half of the
master clock cycle, NWE always goes low (see
The protocol is selected by the DRP field in SMC_CSR
page
Note:
Standard read protocol implements a read cycle during which NRD and NWE are similar. Both
are active during the second half of the clock cycle. The first half of the clock cycle allows time to
ensure completion of the previous access as well as the output of address lines and NCS before
the read cycle begins.
During a standard read protocol, NCS is set low and address lines are valid at the beginning of
the external memory access, while NRD goes low only in the second half of the master clock
cycle to avoid bus conflict. See
196.). Standard read protocol is the default protocol after reset.
In the following waveforms and descriptions NWE represents NWE, NWR0 and NWR1 unless
NWR0 and NWR1 are otherwise represented. In addition, NCS represents NCS[7:0] (see
“I/O Lines” on page
D[15:0]
A[22:0]
NWE
MCK
NCS
163,
Table 22-1
Figure
22-11.
and
Table
Figure 22-18 on page
22-2).
(See “SMC Chip Select Registers” on
173).
6222F–ATARM–14-Jan-11
22.5.1
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