AT91SAM7SE256B-CUR Atmel, AT91SAM7SE256B-CUR Datasheet - Page 202

• Manufacturer Part Number: AT91SAM7SE256B-CUR
• Description: IC ARM7 MCU FLASH 256K 128-LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7SE256B-CUR

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: EBI/EMI, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 88
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: SAM7SE256
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 88
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Processor To Be Evaluated: AT91SAM7SE256B
• Supply Current (max): 60 uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

23.5
23.5.1
202
Product Dependencies
SAM7SE512/256/32 Preliminary
SDRAM Device Initialization
The initialization sequence is generated by software. The SDRAM devices are initialized by the
following sequence:
After initialization, the SDRAM devices are fully functional.
Note:
1. SDRAM Characteristics must be set in the Configuration Register: asynchronous tim-
2. A minimum pause of 200 µs is provided to precede any signal toggle.
3.
4. An All Banks Precharge command is issued to the SDRAM devices. The application
5. Eight auto-refresh (CBR) cycles are provided. The application must set the Mode to 4 in
6. A Mode Register set (MRS) cycle is issued to program the parameters of the SDRAM
7. The application must go into Normal Mode, setting Mode to 0 in the Mode Register and
8. Write the refresh rate into the count field in the SDRAMC Refresh Timer Register.
ings (TRC, TRAS,...), number of columns, rows, and CAS latency. The data bus width
must be set in the Mode Register.
(1)
1 in the Mode Register and perform a write access to any SDRAM address.
must set Mode to 2 in the Mode Register and perform a write access to any SDRAM
address.
the Mode Register and performs a write access to any SDRAM location height times.
devices, in particular CAS latency and burst length. The application must set Mode to 3
in the Mode Register and perform a write access to the SDRAM.
performing a write access at any location in the SDRAM.
(Refresh rate = delay between refresh cycles). The SDRAM device requires a refresh
every 15.625 µs or 7.81 µs. With a 100 MHz frequency, the Refresh Timer Counter
Register must be set with the value 1562(15.652 µs x 100 MHz) or 781(7.81 µs x 100
MHz).
A NOP command is issued to the SDRAM devices. The application must set Mode to
1. It is strongly recommended to respect the instructions stated in step
cess in order to be certain that the following commands issued by the SDRAMC will be well
taken into account.
3
of the initialization pro-
6222F–ATARM–14-Jan-11