AT91SAM7SE256B-CUR Atmel, AT91SAM7SE256B-CUR Datasheet - Page 91
AT91SAM7SE256B-CUR
Manufacturer Part Number
AT91SAM7SE256B-CUR
Description
IC ARM7 MCU FLASH 256K 128-LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7SE256-AU.pdf
(673 pages)
Specifications of AT91SAM7SE256B-CUR
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
EBI/EMI, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
88
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
SAM7SE256
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SPI, USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
88
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 85 C
Processor To Be Evaluated
AT91SAM7SE256B
Supply Current (max)
60 uA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
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Part Number
Manufacturer
Quantity
Price
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18.4.4
18.4.5
6222F–ATARM–14-Jan-11
Abort Status
Memory Protection Unit
There are three reasons for an abort to occur:
When an abort occurs, a signal is sent back to all the masters, regardless of which one has gen-
erated the access. However, only the ARM7TDMI can take an abort signal into account, and
only under the condition that it was generating an access. The Peripheral Data Controller does
not handle the abort input signal. Note that the connection is not represented in
To facilitate debug or for fault analysis by an operating system, the Memory Controller integrates
an Abort Status register set.
The full 32-bit wide abort address is saved in MC_AASR. Parameters of the access are saved in
MC_ASR and include:
In the case of a Data Abort from the processor, the address of the data access is stored. This is
useful, as searching for which address generated the abort would require disassembling the
instructions and full knowledge of the processor context.
In the case of a Prefetch Abort, the address may have changed, as the prefetch abort is pipe-
lined in the ARM processor. The ARM processor takes the prefetch abort into account only if the
read instruction is executed and it is probable that several aborts have occurred during this time.
Thus, in this case, it is preferable to use the content of the Abort Link register of the ARM
processor.
The Memory Protection Unit allows definition of up to 16 memory spaces within the internal
memories. Note that the external memories can not be protected.
After reset, the Memory Protection Unit is disabled. Enabling it requires writing the Protection
Unit Enable Register (MC_PUER) with the PUEB at 1.
Programming of the 16 memory spaces is done in the registers MC_PUIA0 to MC_PUIA15.
The size of each of the memory spaces is programmable by a power of 2 between 1K bytes and
4M bytes. The base address is also programmable on a number of bits according to the size.
The Memory Protection Unit also allows the protection of the peripherals by programming the
Protection Unit Peripheral Register (MC_PUP) with the field PROT at the appropriate value.
The peripheral address space and each internal memory area can be protected against write
and non-privileged access of one of the masters. When one of the masters performs a forbidden
access, an Abort is generated and the Abort Status traces what has happened.
• access to an undefined address
• access to a protected area without the permitted state
• an access to a misaligned address.
• the size of the request (field ABTSZ)
• the type of the access, whether it is a data read or write, or a code fetch (field ABTTYP)
• whether the access is due to accessing an undefined address (bit UNDADD), a misaligned
• the source of the access leading to the last abort (bits MST0 and MST1)
• whether or not an abort occurred for each master since the last read of the register (bit
address (bit MISADD) or a protection violation (bit MPU)
SVMST0 and SVMST1) unless this information is loaded in MST bits
SAM7SE512/256/32 Preliminary
Figure
18-1.
91
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