AT91SAM7SE256B-CUR Atmel, AT91SAM7SE256B-CUR Datasheet - Page 204

• Manufacturer Part Number: AT91SAM7SE256B-CUR
• Description: IC ARM7 MCU FLASH 256K 128-LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7SE256B-CUR

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: EBI/EMI, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 88
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: SAM7SE256
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 88
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Processor To Be Evaluated: AT91SAM7SE256B
• Supply Current (max): 60 uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

23.6
23.6.1
Figure 23-3. Write Burst, 32-bit SDRAM Access
204
D[31:0]
A[12:0]
SDWE
SDCS
SDCK
RAS
CAS
Functional Description
SAM7SE512/256/32 Preliminary
SDRAM Controller Write Cycle
Row n
The SDRAM Controller allows burst access or single access. To initiate a burst access, the
SDRAM Controller uses the transfer type signal provided by the master requesting the access. If
the next access is a sequential write access, writing to the SDRAM device is carried out. If the
next access is a write-sequential access, but the current access is to a boundary page, or if the
next access is in another row, then the SDRAM Controller generates a precharge command,
activates the new row and initiates a write command. To comply with SDRAM timing parameters,
additional clock cycles are inserted between precharge/active (t
(t
Register” on page
t
RCD
RCD
) commands. For definition of these timing parameters, refer to the
= 3
col a
Dna
213. This is described in
col b
Dnb
col c
Dnc
col d
Dnd
col e
Dne
Figure 23-3
col f
Dnf
col g
Dng
below.
col h
Dnh
RP
col i
Dni
) commands and active/write
“SDRAMC Configuration
col j
Dnj
6222F–ATARM–14-Jan-11
col k
Dnk
col l
Dnl