AT91SAM7SE256B-CUR Atmel, AT91SAM7SE256B-CUR Datasheet - Page 197

• Manufacturer Part Number: AT91SAM7SE256B-CUR
• Description: IC ARM7 MCU FLASH 256K 128-LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7SE256B-CUR

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: EBI/EMI, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 88
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: SAM7SE256
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 88
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Processor To Be Evaluated: AT91SAM7SE256B
• Supply Current (max): 60 uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

• DBW: Data Bus Width
• DRP: Data Read Protocol
0: Standard Read Protocol is used.
1: Early Read Protocol is used.
• ACSS: Address to Chip Select Setup
• RWSETUP: Read and Write Signal Setup Time
See definition and description below.
• RWHOLD: Read and Write Signal Hold Time
See definition and description below
Notes:
6222F–ATARM–14-Jan-11
0
0
0
0
1
1
1
1
1. For a visual description, please refer to
2. In Standard Read Protocol.
3. In Early Read Protocol. (It is not possible to use the parameters RWSETUP or RWHOLD in this mode.)
4. When the ECC Controller is used, RWHOLD must be programmed to 1 at least.
RWSETUP
22-46
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
and
(1)
Figure 22-47 on page
ACSS
DBW
0
1
0
1
0
1
0
1
NRD Setup
½ cycle
0 cycles
1 + ½ cycles
2 + ½ cycles
3 + ½ cycles
4 + ½ cycles
5 + ½ cycles
6 + ½ cycles
7 + ½ cycles
0
1
0
1
0
1
0
1
.
(2)
(3)
or
198.
“Setup and Hold Cycles” on page 174
NWR Setup
½ cycle
1 + ½ cycles
2 + ½ cycles
3 + ½ cycles
4 + ½ cycles
5 + ½ cycles
6 + ½ cycles
7 + ½ cycles
Data Bus Width
Reserved
16-bit
8-bit
Reserved
Chip Select Waveform
Standard, asserted at the beginning of the access and deasserted at the end.
One cycle less at the beginning and the end of the access.
Two cycles less at the beginning and the end of the access.
Three cycles less at the beginning and the end of the access.
SAM7SE512/256/32 Preliminary
0
0
0
0
1
1
1
1
RWHOLD
0
0
1
1
0
0
1
1
(1) (4)
and the diagrams in
0
1
0
1
0
1
0
1
NRD Hold
0
1 cycles
2 cycles
3 cycles
4 cycles
5 cycles
6 cycles
7 cycles
Figure 22-45
NWR Hold
½ cycle
1 cycle
2 cycles
3 cycles
4 cycles
5 cycles
6 cycles
7 cycles
and
Figure
197