AT91SAM7SE256B-CUR Atmel, AT91SAM7SE256B-CUR Datasheet - Page 141

• Manufacturer Part Number: AT91SAM7SE256B-CUR
• Description: IC ARM7 MCU FLASH 256K 128-LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7SE256B-CUR

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: EBI/EMI, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 88
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: SAM7SE256
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 88
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Processor To Be Evaluated: AT91SAM7SE256B
• Supply Current (max): 60 uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

21.5
21.5.1
21.6
21.6.1
21.6.2
21.6.3
21.6.4
21.6.5
6222F–ATARM–14-Jan-11
Product Dependencies
Functional Description
I/O Lines
Bus Multiplexing
Static Memory Controller
SDRAM Controller
ECC Controller
CompactFlash Support
The pins used for interfacing the External Bus Interface may be multiplexed with the PIO lines.
The programmer must first program the PIO controller to assign the External Bus Interface pins
to their peripheral function. If I/O lines of the External Bus Interface are not used by the applica-
tion, they can be used for other purposes by the PIO Controller.
The EBI transfers data between the internal ASB Bus (handled by the Memory Controller) and
the external memories or peripheral devices. It controls the waveforms and the parameters of
the external address, data and control busses and is composed of the following elements:
The EBI offers a complete set of control signals that share the 32-bit data lines, the address
lines of up to 23 bits and the control signals through a multiplex logic operating in function of the
memory area requests.
Multiplexing is specifically organized in order to guarantee the maintenance of the address and
output control lines at a stable state while no external access is being performed. Multiplexing is
also designed to respect the data float times defined in the Memory Controllers. Furthermore,
refresh cycles of the SDRAM are executed independently by the SDRAM Controller without
delaying the other external Memory Controller accesses.
For information on the Static Memory Controller, refer to the Static Memory Controller Section.
For information on the SDRAM Controller, refer to the SDRAMC Section.
For information on the ECC Controller, refer to the ECCC Section.
The External Bus Interface integrates circuitry that interfaces to CompactFlash devices.
The CompactFlash logic is driven by the Static Memory Controller (SMC) on the NCS4 and/or
NCS2 address space. Programming the CS4A and/or CS2A bit of the Chip Select Assignment
Register
enables this logic. Access to an external CompactFlash device is then made by accessing the
• The Static Memory Controller (SMC)
• The SDRAM Controller (SDRAMC)
• The ECC Controller (ECC)
• A chip select assignment feature that assigns an ASB address space to the external devices
• A multiplex controller circuit that shares the pins between the different Memory Controllers
• Programmable CompactFlash support logic
• Programmable NAND Flash support logic
(See “EBI Chip Select Assignment Register” on page
SAM7SE512/256/32 Preliminary
158.) to the appropriate value
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