LFXP2-17E-5FN484I Lattice, LFXP2-17E-5FN484I Datasheet - Page 145

• Manufacturer Part Number: LFXP2-17E-5FN484I
• Description: FPGA - Field Programmable Gate Array 17K LUTs 358 I/O Ins on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-17E-5FN484I

• Number Of Macrocells: 17000
• Number Of Programmable I/os: 358
• Data Ram Size: 282624
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-484
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 282624
• Number Of I /o: 358
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
OSC Usage with VHDL - Example
COMPONENT OSCE
END COMPONENT;
begin
OSCInst0: OSCE
OSC Usage with Verilog - Example
module OSC_TOP(OSC_CLK);
output OSC_CLK;
OSCE OSCinst0 (.OSC(OSC_CLK));
endmodule
Setting Clock Preferences
Designers can use clock preferences to implement clocks to the desired performance. Preferences can be set in
the Pre-Map Preference Editor (Design Planner) or in preference files. Frequently used preferences are described
in Appendix C.
Power Supplies
Each PLL has its own power supply pin, VCCPLL. Since VCCAUX and VCCPLL are normally the same 3.3V, it is
recommended that they are driven from the same power supply on the circuit board, thus minimizing leakage. In
addition, each of these supplies should be independently isolated from the main 3.3V supply on the board using
proper board filtering techniques to minimize the noise coupling between them.
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
e-mail:
Internet:
Revision History
February 2007
February 2010
PORT (OSC:OUT
PORT MAP ( OSC=>
[phone] (Outside North America)
[e-mail]
www.latticesemi.com
Date
std_logic);
osc_int);
Version
01.0
01.1
Initial release.
Reconciled LOCK description among MachXO, LatticeXP2,
LatticeECP2/M and LatticeECP3.
9-23
Change Summary
LatticeXP2 sysCLOCK PLL
Design and Usage Guide