LFXP2-17E-5FN484I Lattice, LFXP2-17E-5FN484I Datasheet - Page 336

• Manufacturer Part Number: LFXP2-17E-5FN484I
• Description: FPGA - Field Programmable Gate Array 17K LUTs 358 I/O Ins on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-17E-5FN484I

• Number Of Macrocells: 17000
• Number Of Programmable I/os: 358
• Data Ram Size: 282624
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-484
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 282624
• Number Of I /o: 358
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Power Supply Ramp
Similar to the power supply sequencing, there is no specific requirement for the LatticeXP2 but care must be given
to the power supply ramp times in a reasonable range. The reasonable range is defined by the majority of the
power supply related device test data taken as part of the device characterization. The fast end of the spectrum is
defined to be 100µs for the supply to transition from zero volts to minimum supply voltage level. The slow end of the
spectrum is defined to be 100ms for the supply to transition from zero volts to minimum supply voltage. These
ranges should be used as general guidelines for the system design consideration.
Power Estimation
Once the LatticeXP2 device density, package and logic implementation is decided, power estimation for the system
environment should be determined based on the software Power Calculator provided as part of ispLEVER
tool. The power estimation should keep two specific goals in mind.
By determining these two criteria, system design planning can take the LatticeXP2 power requirements into con-
sideration early in the design phase.
Configuration
There are two options to configure the LatticeXP2 devices. The obvious and most common method is using the on-
chip Flash memory. This method is called the Self Download Mode or SDM. The SDM is determined by the CFG0
signal. CFG0 needs to be pulled high in order to boot the device from the on-chip flash memory. External pull-up
resistor highly recommended pulling up the CFG0 signal to the 3.3V supply rail. Table 18-2 shows the proper CFG
bit setting.
Table 18-2. Configuration Mode Selection
The SPI configuration port resides in I/O bank 7. Accordingly, the V
Flash. For example, if the external SPI Flash uses 3.3V rail, V
There are several dual-purpose pins that can be used as general-purpose I/O pins when not used for configuration.
Table 18-3 lists these dual-purpose pins. When CFGx is set to one of the two external SPI flash options and persis-
tence is OFF, the dual-purpose configuration pins will become general-purpose I/O pins after configuration. These
pins should be used only when they are not used for configuration. When used for configuration, persistence
should be ON, to dedicate these pins for configuration. In order to insure proper configuration, it is recommended to
use external resistors for the configuration pins. The CFG0 must have external resistor for any configuration mode.
When CFG0=0, CFG1, PROGRAMN, INITN and DONE pins must have the appropriate external pull-up or pull-
down resistors.
SPI Flash Boot
Embedded Flash Boot
Self Download Mode (SDM)
Configuration Mode
1. Power supply budgeting should be considered based on the maximum of the power-up in-rush current,
2. The ability for the system environment and LatticeXP2 device packaging to be able to support the specified
configuration current or maximum DC and AC current for given system environmental condition.
maximum operating junction temperature.
CFG1
X
0
1
CFG0
0
0
1
Master SPI Boot first then embedded Flash.
Embedded flash boot first then external SPI Flash.
SDM only.
18-2
CCIO7
must be tied to 3.3V supply rail as well.
CCIO7
LatticeXP2 Hardware Checklist
must match the supply rail of the SPI
Description
®
design