LFXP2-17E-5FN484I Lattice, LFXP2-17E-5FN484I Datasheet - Page 310

• Manufacturer Part Number: LFXP2-17E-5FN484I
• Description: FPGA - Field Programmable Gate Array 17K LUTs 358 I/O Ins on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-17E-5FN484I

• Number Of Macrocells: 17000
• Number Of Programmable I/os: 358
• Data Ram Size: 282624
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-484
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 282624
• Number Of I /o: 358
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Note that the calculated CRC is based on the particular arrangement of configuration memory for a particular
design. Consequently, the expected CRC results cannot be specified until after the design is placed and routed.
The ispLEVER
updates the 32-bit SED CRC register contents during bitstream generation.
The following sections describe the LatticeXP2 SED implementation and flow, along with some sample code to get
started with.
Basic SED and One-shot SED Modes
Basic SED
Basic SED checks the CRC for all bits. For Basic SED (SEDBA), the inputs are SEDCLKIN, SEDENABLE, SED-
START, and SEDFRCERRN. The output signals are SEDCLKOUT, SEDDONE, SEDINPROG, and SEDERR.
Once an error is detected the SEDERR signal will stay high. SED supports the following Soft Error Corrections
(SEC): “Do Nothing” or on-demand user reconfiguration by pulling the PROGAMN pin low from another device.
One-Shot SED
The One-Shot SED setting is based on the One-Shot Fuse. The module (SEDBB) has no input ports. The output
signals are SEDDONE, SEDINPROG, and SEDERR. At a minimum, the user must connect SEDERR to an I/O pin
in order to detect an error.
Hardware Description
As shown in Figure 16-2, the LatticeXP2 SED hardware has several inputs and outputs that allow the user to con-
trol, and monitor, SED behavior.
Figure 16-2. Signal Block Diagram
Signal Descriptions
Table 16-1. SED Signal Descriptions
®
bitstream generation software analyzes the configuration of a placed and routed design and
SEDCLKIN
SEDENABLE
SEDCLKOUT
SEDSTART
SEDINPROG
SEDDONE
SEDFRCERRN
SEDERR
Signal Name
SEDENABLE
SEDSTART
SEDFRCERRN
SEDCLKIN
(From Internal
Oscillator)
Direction
Output
Output
Output
Output
Input
Input
Input
Input
Hardware
Block
16-2
SED
Active
High
High
High
High
High
Low
N/A
N/A
SEDCLKOUT
SEDDONE
SEDINPROG
SEDERR
Clock
SED enable
Output clock
Start SED cycle
SED cycle is in progress
SED cycle is complete
Force an SED error flag
SED error flag
Description
Detection Usage Guide
LatticeXP2 Soft Error