LFXP2-17E-5FN484I Lattice, LFXP2-17E-5FN484I Datasheet - Page 178
LFXP2-17E-5FN484I
Manufacturer Part Number
LFXP2-17E-5FN484I
Description
FPGA - Field Programmable Gate Array 17K LUTs 358 I/O Ins on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFXP2-8E-5FTN256I.pdf
(341 pages)
Specifications of LFXP2-17E-5FN484I
Number Of Macrocells
17000
Number Of Programmable I/os
358
Data Ram Size
282624
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-484
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
282624
Number Of I /o
358
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-17E-5FN484I
Manufacturer:
Lattice
Quantity:
175
Company:
Part Number:
LFXP2-17E-5FN484I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Figure 10-29. FIFO with Output Registers and RdEn on Output Registers
Dual Clock First In First Out (FIFO_DC) Memory:
The FIFO_DC or the dual clock FIFO is also an emulated FIFO. Again, the address logic and the flag logic is imple-
mented in the FPGA fabric around the RAM.
The ports available on the FIFO_DC are:
• Reset
• RPReset
• WrClock
• RdClock
• WrEn
• RdEn
• Data
• Q
• Full Flag
• Almost Full Flag
• Empty Flag
• Almost Empty Flag
FIFO_DC Flags
The FIFO_DC, as an emulated FIFO, required the flags to be implemented in the FPGA logic around the block
RAM. Because of the two clocks, the flags were required to change clock domains from read clock to write clock
and vice versa. This adds latency to the flags either during assertion or de-assertion. The latency can be avoided
only in one of the cases (either assertion or de-assertion) or distributed among these cases.
In the current emulated FIFO_DC, there is no latency during assertion of these flags which we feel is more impor-
tant. Thus, when these flags are required to go true, there is no latency. However, due to the design of the flag logic
running on two clock domains, there is latency during the de-assertion.
Almost
Almost
Empty
Empty
Reset
Clock
WrEn
RdEn
Data
Full
Full
Q
Invalid Data
Data_1
Invalid Data
Data_2
10-28
Data_3
Data_4
LatticeXP2 Memory Usage Guide
Data_1
Data_5
Data_2
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