LFXP2-17E-5FN484I Lattice, LFXP2-17E-5FN484I Datasheet - Page 297

• Manufacturer Part Number: LFXP2-17E-5FN484I
• Description: FPGA - Field Programmable Gate Array 17K LUTs 358 I/O Ins on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-17E-5FN484I

• Number Of Macrocells: 17000
• Number Of Programmable I/os: 358
• Data Ram Size: 282624
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-484
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 282624
• Number Of I /o: 358
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Tag Memory
The TAG Memory is a block of Flash memory which is always available for read or write (programming in Flash
terms) through the Slave SPI port. The LatticeXP2 can be in user mode or an un-programmed state (blank device),
independent of the CFG[1:0] pin setting. The only exceptions would be when the LatticeXP2 is in BSCAN test or in
direct programming mode. During these modes the SPI interface is unavailable because the I/O is under BSCAN
control.
The TAG memory is also available through the JTAG port.
Table 14-10 shows the amount of Tag memory available in each LatticeXP2 device. Each LatticeXP2 device has
one dedicated row of TAG memory.
Table 14-10. LatticeXP2 Family TAG Memory
Note: The Initial Power on Value (INITVAL) for all Flash cells is all 1's.
The TAG memory has the following features and limitations.
• Each row of TAG memory is limited to sequential access only. Once the read command is specified, the entire
• Data access speed is limited by the speed of the TAG memory which is Flash based.
• The TAG memory comes from the factory erased. It will retain the user assigned value after programming even
• The TAG memory can be read or written using the hardwired JTAG and SPI interface pins.
• The TAG memory is ready to use upon power-up of the LatticeXP2. It does not need any software IP or design
• The TAG memory can also be read and modified from the FPGA core logic using the slave-SPI CIB interface
• The TAG memory is always accessible regardless of the security setting of the device.
The TAG memory is designed for storing typically “static” data - data that is not likely to change. This TAG memory
can take the place of an EEPROM or simple Flash memory on the PCB which might be used for the following sys-
tem management and manufacturing control information (listed as examples only):
• Saving Electronic ID codes
• Version management
• Date stamping
• Manufacturing version control
• Asset management and tracking
• System calibration settings
• Device serialization and/or inventory control.
TAG memory contents are read sequentially in a first-in-first-out manner.
during power off periods.
loaded into the device to access the TAG memory via the hardwired interface.
pins to emulate an I
2
C port.
Device Density
XP2-17
XP2-30
XP2-40
XP2-5
XP2-8
Tag Memory (Bits)
14-15
2184
2640
3384
632
768
LatticeXP2 sysCONFIG Usage Guide
Tag Memory (Bytes)
273
330
423
79
96