LFXP2-17E-5FN484I Lattice, LFXP2-17E-5FN484I Datasheet - Page 149

• Manufacturer Part Number: LFXP2-17E-5FN484I
• Description: FPGA - Field Programmable Gate Array 17K LUTs 358 I/O Ins on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-17E-5FN484I

• Number Of Macrocells: 17000
• Number Of Programmable I/os: 358
• Data Ram Size: 282624
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-484
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 282624
• Number Of I /o: 358
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
USE EDGE
Use a edge clock resource to route the specified net:
CLOCK_TO_OUT
Specifies a maximum allowable output delay relative to a clock.
Here are two preferences using both the CLKPORT and CLKNET keywords showing the corresponding scope of
TRACE reporting.
The CLKNET will stop tracing the path before the PLL, so you will not get PLL compensation timing numbers.
The above preference will yield the following clock path:
If CLKPORT is used, the trace is complete back to the clock port resource and provides PLL compensation timing
numbers.
The above preference will yield the following clock path:
INPUT_SETUP
Specifies an setup time requirement for input ports relative to a clock net.
PLL_PHASE_BACK
This preference is used with INPUT_SETUP when a user needs a trace calculation based on the previous clock
edge.
This preference is useful when setting the PLL output phase adjustment. Since there is no negative phase adjust-
ment provided, the PLL_PHASE_BACK preference works as if negative phase adjustment is available.
USE EDGE NET “clk_fast”;
CLOCK_TO_OUT PORT “RxAddr_0” 6.000000 ns CLKNET “pll_rxclk” ;
Clock path pll_inst/pll_utp_0_0 to PFU_33:
Name
ROUTE
CLOCK_TO_OUT PORT “RxAddr_0” 6.000000 ns CLKPORT “RxClk” ;
Clock path RxClk to PFU_33:
Name
IN_DEL
ROUTE
MCLK_DEL
ROUTE
INPUT_SETUP
PLL_PHASE_BACK ;
--------
--------
8.771
Fanout
49
Fanout
---
1
---
49
2.892
PORT
(57.4% logic, 42.6% route), 2 logic levels.
(0.0% logic, 100.0% route), 0 logic levels.
“datain”
Delay (ns)
2.892
Delay (ns)
1.431
0.843
3.605
2.892
2.000000
Site
ULPPLL.MCLK to R3C14.CLK0 pll_rxclk
Site
D5.PAD to
D5.INCK to
ULPPLL.CLKIN to ULPPLL.MCLK pll_inst/pll_utp_0_0
ULPPLL.MCLK to R3C14.CLK0 pll_rxclk
9-27
ns
HOLD
Resource
Resource
D5.INCK RxClk
ULPPLL.CLKIN RxClk_c
1.000000
LatticeXP2 sysCLOCK PLL
Design and Usage Guide
ns
CLKPORT
“clk”