LFXP2-17E-5FN484I Lattice, LFXP2-17E-5FN484I Datasheet - Page 300

• Manufacturer Part Number: LFXP2-17E-5FN484I
• Description: FPGA - Field Programmable Gate Array 17K LUTs 358 I/O Ins on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-17E-5FN484I

• Number Of Macrocells: 17000
• Number Of Programmable I/os: 358
• Data Ram Size: 282624
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-484
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 282624
• Number Of I /o: 358
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LatticeXP2 Configuration Encryption
and Security Usage Guide
May 2008
Technical Note TN1142
Introduction
Unlike a volatile FPGA, which requires an external boot-prom to store configuration data, the LatticeXP2™ devices
are non-volatile and have on-chip configuration Flash. Once programmed (either by JTAG or SPI port), this data is
a part of the FPGA device and can be used to self-download the SRAM portion without requiring any additional
external boot prom. Hence it is inherently more secure than volatile FPGAs. Like the LatticeECP2/M, the
LatticeXP2 family also offers the 128-bit Advanced Encryption Standard (AES) to protect the externally stored pro-
gramming file. The user has total control over the 128-bit key and no special voltages are required to maintain the
key within the FPGA. Additional security enhancement for the LatticeXP2 includes:
• A security bit for the Configuration and User Flash
• One-Time-Programmable (OTP) or Permanent Lock capability
• Flash Protect
This document explains the encryption and security features and how to take advantage of them.
Encryption/Decryption Flow
The LatticeXP2 supports both encrypted and non-encrypted JEDEC files. Since the non-encrypted flow is covered
in TN1141,
LatticeXP2 sysCONFIG™ Usage
Guide, this document will concentrate on the additional steps needed
for the encrypted flow. The encrypted flow adds only two steps to the normal FPGA design flow, encryption of the
configuration JEDEC file and programming the encryption key into the LatticeXP2. Figure 15-1 is a block diagram
describing the LatticeXP2 encryption data paths that will be used throughout this document.
Figure 15-1. Encryption Block Diagram along with Flash Protect
SRAM
AES Encrypt Enable
128-Bit Flash Decryption Key
Data Shift Register
AES
Encrypted Data
Decrypted Data
CRC
64-Bit Flash
Enable Key
Configuration Flash
Flash Protect Key
Configuration Flash
Program Enable
Encrypting the JEDEC File
®
As with any other Lattice FPGA design flow, the design engineer must first create the design using the ispLEVER
design tool suite. The design is synthesized, mapped, placed and routed, and verified. Once the user is satisfied
with the design, the final JEDEC file is ready for FPGA programming. This final JEDEC file is used to secure the
design.
The JEDEC file can be encrypted using ispLEVER by going to the Tools -> Security Settings pull-down menu or
®
by using the Universal File Writer (ispUFW), which is part of the Lattice ispVM
System tool suite.
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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15-1
tn1142_01.1