LFXP2-17E-5FN484I Lattice, LFXP2-17E-5FN484I Datasheet - Page 212

• Manufacturer Part Number: LFXP2-17E-5FN484I
• Description: FPGA - Field Programmable Gate Array 17K LUTs 358 I/O Ins on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-17E-5FN484I

• Number Of Macrocells: 17000
• Number Of Programmable I/os: 358
• Data Ram Size: 282624
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-484
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 282624
• Number Of I /o: 358
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
IDDRMX1A
This primitive will implement the input register block in memory mode. The DDR registers are designed to use edge
clock routing on the I/O side and the primary clock on the FPGA side. The ECLK input is used to connect to the
DQS strobe coming from the DQS delay block (DQSBUFC primitive). The SCLK input is connected to the system
(FPGA) clock. DDRCLKPOL is an input from the DQS Clock Polarity tree. This signal is generated by the DQS
Transition detect circuit in the hardware. The DDRCLKPOL signal is used to choose the polarity of the SCLK to the
synchronization registers.
Figure 11-10. IDDRMX1A Symbol
Table 11-3 provides a description of all I/O ports associated with the IDDRMX1A primitive.
Table 11-3. IDDRMX1A Ports
Figure 11-11 shows the Input Register Block configured in the IDDRMX1A mode.
D
ECLK
RST
SCLK
CE
DDRCLKPOL
QA
QB
Note:
DQSBUFC.
Port Name
The DDRCLKPOL input to IDDRMX1A should be connected to the DDRCLKPOL output of
I/O
O
O
I
I
I
I
I
I
DDR Data
Reset
System CLK
Clock enable
DDR clock polarity signal
Data at Positive edge of the CLK
Data at the negative edge of the CLK
The phase shifted DQS should be connected to this input
ECLK
RST
SCLK
CE
DDRCLKPOL
D
IDDRMX1A
11-8
QA
QB
Definition
LatticeXP2 High-Speed I/O Interface