LFXP2-17E-5FN484I Lattice, LFXP2-17E-5FN484I Datasheet - Page 198

• Manufacturer Part Number: LFXP2-17E-5FN484I
• Description: FPGA - Field Programmable Gate Array 17K LUTs 358 I/O Ins on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-17E-5FN484I

• Number Of Macrocells: 17000
• Number Of Programmable I/os: 358
• Data Ram Size: 282624
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-484
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 282624
• Number Of I /o: 358
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Delay time = 20 x 1/frequency.
The transfer delay time, including the extra delay time to enable the Flash circuitry, is 5uS minimum. The clock fre-
quency can then be set to 2.5 MHz if continuous clocking is desired.
When all the data captured into the data buffer are shifted out, additional clocks will shift out dummy data. The SI
pin is not connected to the input of the data buffer when the READ_TAG command is shifted into the device. While
the data in the data buffer is shifted out to the direction of SO, dummy data is shifted into the data buffer. Conse-
quently, when over-shifting occurs, dummy data of unknown value is shifted out.
Figure 10-57. Readout Order
Figure 10-58. READ_TAG Waveform
STATUS (4Ah)
The STATUS command allows the single-bit status register to be read. This command can be loaded at any time
after the WRITE_EN command has already been shifted into the device first. This command does not terminate
the programming or erase action. It is used to report the progress of the programming or erase action.
The status register actual size is only 1 bit. Dummy data is shifted out on the SO pin if extra data shifting clocks are
applied. The command can be shifted into the device again to capture the status bit and then read out.
During the interval of shifting the command, the additional programming or erase time is provided by driving the
Chip Select pin to high and holding the CLK pin low. Clocking while holding the Chip Select pin high is optional.
If the maximum programming time or erasure has expired and the status bit still is not set to 1, then erase or pro-
gramming has failed.
CS
CLK
SI
SO
Cell N-1
Flash
8 Bits READ_TAG
Command
Bit N-1
Bit N-1
Time elapsed must be 5µs
24 Bits Dummy
Flash Memory Cells
HI-Z
If the clock is too fast
add delay before
Data capture
21st clock
21st clock
starts at
10-48
0 1 2
LatticeXP2 Memory Usage Guide
TAG Memory Data
Enable SO on 24th Dummy Clock.
Bit 0 is valid.
Bit 0
Bit 0
Cell 0
Flash
SO
N-1
HI-Z