LFXP2-17E-5FN484I Lattice, LFXP2-17E-5FN484I Datasheet - Page 328

• Manufacturer Part Number: LFXP2-17E-5FN484I
• Description: FPGA - Field Programmable Gate Array 17K LUTs 358 I/O Ins on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-17E-5FN484I

• Number Of Macrocells: 17000
• Number Of Programmable I/os: 358
• Data Ram Size: 282624
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-484
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 282624
• Number Of I /o: 358
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 17-3. Procedure for Converting a JEDEC File to a Bitstream using the ispUFW (Continued)
Once the bitstream is generated, follow the procedures shown in Figure 17-2 and Table 17-4 to program the bit-
stream into the SPI Flash device on ispVM System. ispVM System supports quite many useful SPI Flash opera-
tions. Most operations are intuitively understood by users thus do not require detail description in this document.
After the SPI Flash is programmed with a valid bitstream, and if the LatticeXP2 device is not yet programmed,
using JTAG refresh or power cycling the LatticeXP2 device will activate the Master SPI port to boot from the SPI
Flash device. The PROGRAMN pin will work as long as the JTAG port has not been used. If the JTAG port has
been used, power cycle the LatticeXP2 device will re-enable the PROGRAMN pin. Please refer to Critical Point 2
above for more details.
The mechanical detail on the JTAG port in the LatticeXP2 device serving as a SPI host to access the external SPI
Flash devices can be found in the reference section at the end of this document.
Figure 17-2. Using ispVM to Program a Bitstream into the SPI Flash Device
Steps
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This is optional. The default is 2.5 MHz. The maximum frequency recommended is 15 MHz due to the +/- 30%
variance of the clock oscillator of the LatticeXP2 devices and the typical slow read (opcode = 0x03) frequency is
20 MHz maximum of the SPI Flash devices.
The other settings following the Frequency shall be left to default to as shown. Just for completeness, the purpose
of the other settings are described below:
Ignore ID Code = Insert the LatticeXP2 device 32-bit Device ID checking into the bitstream. Default = do not check
IDCODE.
Program Secure = Insert the program security fuse command into the bitstream. Default = per the JEDEC file G
field setting.
Disable CRC Calculation = Remove CRC checking in the bitstream. OFF = the bitstream has CRC checking.
(Note: The LatticeXP2 devices use the CRC value to check against bitstream corruption for configuration pass/fail
decision. User must not change this setting when generating the final customer ready bitstream. These features
are provided to aid board development and debugging.)
Click the file generation button to generate the bitstream.
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17-10
Description
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LatticeXP2 Dual Boot Feature
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