LFXP2-17E-5FN484I Lattice, LFXP2-17E-5FN484I Datasheet - Page 155

• Manufacturer Part Number: LFXP2-17E-5FN484I
• Description: FPGA - Field Programmable Gate Array 17K LUTs 358 I/O Ins on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-17E-5FN484I

• Number Of Macrocells: 17000
• Number Of Programmable I/os: 358
• Data Ram Size: 282624
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-484
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 282624
• Number Of I /o: 358
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
LatticeXP2 Memory Usage Guide
Figure 10-4. Example Generating Pseudo Dual Port RAM (RAM_DP) Module Customization
The left side of this window shows the block diagram of the module. The right side includes the Configuration tab
where users can choose options to customize the RAM_DP (e.g. specify the address port sizes and data widths).
Users can specify the address depth and data width for the Read Port and the Write Port in the text boxes pro-
vided. In this example, we are generating a Pseudo Dual Port RAM of size 512 x 16. Users can also create RAMs
of different port widths for Pseudo Dual Port and True Dual Port RAMs.
The Input Data and the Address Control are always registered, as the hardware only supports the clocked write
operation for the EBR based RAMs. The check box Enable Output Registers inserts the output registers in the
Read Data Port. Output registers are optional for EBR-based RAMs.
Users have the option to set the Reset Mode as Asynchronous Reset or Synchronous Reset. Enable GSR can be
checked to enable the Global Set Reset.
Users can also pre-initialize their memory with the contents specified in the Memory File. It is optional to provide
this file in the RAM; however for ROM, the Memory File is required. These files can be of Binary, Hex or Addresses
Hex format. The details of these formats are discussed in the Initialization File section of this document.
At this point, users can click the Generate button to generate the module they have customized. A VHDL or Verilog
netlist is then generated and placed in the specified location. Users can incorporate this netlist in their designs.
Another important button is the Load Parameters button. IPexpress stores the parameters specified in a
<module_name>.lpc file. This file is generated along with the module. Users can click on the Load Parameters but-
ton to load the parameters of a previously generated module to re-visit or make changes to them.
Once the module is generated, users can either instantiate the *.lpc or the Verilog-HDL/ VHDL file in top-level mod-
ule of their design.
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