LFXP2-17E-5FN484I Lattice, LFXP2-17E-5FN484I Datasheet - Page 321

• Manufacturer Part Number: LFXP2-17E-5FN484I
• Description: FPGA - Field Programmable Gate Array 17K LUTs 358 I/O Ins on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-17E-5FN484I

• Number Of Macrocells: 17000
• Number Of Programmable I/os: 358
• Data Ram Size: 282624
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-484
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 282624
• Number Of I /o: 358
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Methods 3 and 4 are of no interest as far as field upgrade is concerned. Therefore, this document will focus only on
methods 1 and 2.
Figure 17-3. Four Methods for Programming the SPI Flash Device
Definitions
SPI
SPI stands for the Serial Peripheral Interface defined originally by Motorola.
Master SPI
The FPGA device boots itself by acting as the SPI host to clock bitstream data out of the external SPI Flash device.
SDM (Self Download Mode)
The FPGA device boots itself in a massive parallel fashion from the embedded Flash for instant-on.
Erase
Write into all the Flash cells state a logical one (1) (a.k.a. open fuse).
Program
Write into the selected Flash cells state a logical zero (0) (a.k.a. close fuse).
Configure
Write the pattern into the SRAM fuses of the FPGA device and wake up. It is also known as boot up.
Primary Boot
Upon power cycling, the FPGA device will load this pattern in first. Only one primary pattern is allowed.
Golden Boot
The guaranteed good pattern loaded into the FPGA device when booting failure occurs. It is also known as the root
boot. Only one Golden boot pattern is allowed.
4. Use off board programming method such as the third party programmers from BPM Microsystems or Sys-
1
2
tem General to pre-program the SPI Flash devices and then mount them on board.
ispVME
CPU
System
ispVM
TCK
TDI
TMS
TDO
JTAG
SHIFT_DR_CSN
SHIFT_DR_TDO
SHIFT_DR_TCK
SHIFT_DR_TDI
LatticeXP2
17-3
CSSPIN
PROGRAM_SPI
IO
IO
IO
3
1
2
1
0
LatticeXP2 Dual Boot Feature
CCLK
SISPI
CSSPIN
SPISO
Note:
The CSSPIN pin is dedicated when the
CFGO pin is set to 0 to enable the dual
boot feature.
Driver
CPU
SPI
SCLK
4 GPIO
CSN
SO
SI
Flash
SPI
4