CR16MCS9VJE8 National Semiconductor, CR16MCS9VJE8 Datasheet
CR16MCS9VJE8
Specifications of CR16MCS9VJE8
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CR16MCS9VJE8 Summary of contents
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... Wire/SPI USART Please note that not all family members contain same peripheral modules and features. TRI-STATE® registered trademark of National Semiconductor Corporation. ©2001 National Semiconductor Corporation plex Instruction Set Computer (CISC): compact code, on- chip memory and I/O, and reduced cost. The CPU uses a ...
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Table of Contents 1.0 General Description 2.0 Features . . ...
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General Description The device has up to 64K bytes of reprogrammable flash EE- PROM program memory or ROM memory, 1.5K bytes of flash EEPROM In-System-Programming memory, 3K bytes of static RAM, 2K bytes of non-volatile EEPROM data mem- ory ...
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... VTU - + represented when - +125 C is represented when CR16 CompactRISC Microcontroller with CAN Interface Family Devices National Semiconductor currently offers a variety of the CR16 CompactRISC Microcontrollers with CAN interface. The CR16MCS offer complete functionality in an 80-pin PQFP package. 4 Temp. Package Peripherals Range ...
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Device Overview The devices are complete microcomputers with all system timing, interrupt logic, program memory, data memory, and I/ O ports included on-chip, making it well-suited to a wide range of embedded controller applications. 3.1 CR16B CPU CORE The ...
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INTERRUPTS The Interrupt Control Unit (ICU31L) receives interrupt re- quests from internal and external sources and generates in- terrupts to the CPU. An interrupt is an event that temporarily stops the normal flow of program execution and causes a ...
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... C and is designed to take full advantage of the CompactRISC architecture. There are In-System Emulation (ISE) devices available for the device from iSYSTEM™, as well as lower-cost evaluation boards. See your National Semiconductor sales representa- tive for current information on availability and features of em- ulation equipment and evaluation boards. 7 ...
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Device Pinouts Pin Name PH4 PH5 PH6 PH7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 ENV0/CLKOUT1 SDA SCL GND Vcc GND CANTx CANRx PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PG7 PG6 PG5 PG4 PG3 PG2 PG1 ...
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Table 1 Package Pin Assignments Pin Name Alternate Function(s) PF0 NMI X1CKO X1CKI GND Vcc GND X2CKO X2CKI 2 RESET PI0 ACH0 PI1 ACH1 PI2 ACN2 PI3 ACH3 PI4 ACH4 PI5 ACH5 PI6 ACH6 PI7 ACH7 Vref AGND AVcc PH0 ...
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PIN DESCRIPTION Some pins have alternate functions which may be enabled. These pins can be individually configured as general pur- pose pins, even when the module they belong to is enabled. Signal Type Active Pin (* for a shared ...
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Pin (* for Signal Type Active a shared pin) TDX1 CMOS High * TDX2 CMOS High * CANTx CMOS High Pin (* for a Signal Type Active shared pin) PF[0:7] CMOS High * PG[0:7] CMOS High * PB[0:7] CMOS High ...
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System Configuration The device has two input pins, ENV0 and ENV1, which are used to specify the operating environment of the device upon reset. There are also two system configuration registers, called the Module Configuration (MCFG) register and the ...
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Input/Output Ports Each device has software-configurable I/O pins, or- ganized into seven ports eight pins per port. The ports are named Port B, Port C, Port F, Port G, Port H, Port I, ...
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Port Alternate Function Register Each port that supports an alternate function (any port other than Port B or Port C) has an alternate function register (Px- ALT). This register determines whether the port pins are used for general-purpose I/O ...
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CPU and Core Registers The device uses the same CR16B CPU core as other Com- pactRISC family members. The core's Reduced Instruction Set Computer (RISC) architecture allows a processing rate one instruction per clock cycle. The ...
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I bit The Global Maskable Interrupt Enable (I) bit is used to enable or disable maskable interrupts. If this bit and the Local Maskable Interrupt En- able (E) bit are both set to 1, all maskable inter- rupts are accepted. ...
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For detailed information on all instructions, see the CompactRISC CR16B Programmer's Reference manual. Table 7 Device Instruction Set Summary Mnemonic Description ADDi Add Integer ADDUi Add Unsigned Integer ADDCi Add Integer with Carry ANDi Bitwise Logical AND ASHUi Arithmetic Shift ...
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Bus Interface Unit The Bus Interface Unit (BIU) controls the interface between the internal core bus and those on-chip modules which are mapped into BIU zones. These on-chip modules are the flash EEPROM program memory, the ISP-memory and the ...
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The IOCFG register address is F902 hex. Upon reset, the register is initialized to 069F hex. The register format is shown below Reserved Reserved HOLD WAIT Memory Wait ...
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T hold cycles to 11 binary for three T hold clock cycles. These bits are ig- nored if the SZCFG0.FRE bit is set Bus Width. ...
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Access Timing Summary Table Table8 is a summary showing the number of access cycles used for various address ranges. Address Memory or Range (hex) I/O Type 0000-BFFF Flash EEPROM Program Memory C000-CBFF Static RAM Memory F000-F27F EEPROM Data Memory ...
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Memory The CompactRISC architecture supports a uniform linear ad- dress space of 2 megabytes, addressed by 21 bits. The de- vice implementation of this architecture uses only the lowest 128K bytes of address space. Each memory location con- tains ...
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All program and erase operations must be preceded immediately by writing the proper key to the pro- gram memory key register PGMKEY. The flash ...
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A similar (but separate) prescaler factor is applied to the EE- PROM data memory. See Section9.1.7 and Section9.3.4 for details. ...
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Program Memory Erase Time Reload Register (FLERASE) The FLERASE register is a byte-wide read/write register that controls the erase pulse width. This value is loaded into the upper 8 bits of the flash timing counter, and at the same ...
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The device hardware internally generates the voltages and timing signals necessary for programming. No additional power supply is required, nor any software required except to check ...
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Data Memory Erase Time Reload Register (DMERASE) The DMERASE register is a byte-wide read/write register that controls the erase pulse width. This value is loaded into the upper 8 bits of the flash timing counter, and at the same ...
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ISP flash EEPROM program memory is being programmed. The ISP flash memory is divided into 192 pages, each page containing 4 words (each 16 bits wide). Each page is further divided into two rows. Erase is carried ...
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EEPROM data memory (F000 to F07E) and the ISP flash EEPROM program memory (E000 to E5FE) can be erased. Read/write is overridden through PADX. E5FC Byte Upon reset of the ...
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When BOOTAREA has any value other than 7F memory (BOOTAREA 128)+15 is considered as user boot ROM area and is write protected. When it has a value then there is no user boot ROM ...
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Interrupts The Interrupt Control Unit (ICU31L) receives interrupt re- quests from internal and external sources and generates in- terrupts to the CPU. Interrupts from the timers, USARTs, MICROWIRE/SPI interface, Multi-Input Wake-Up, and A/D converter are all maskable interrupts. The ...
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Table 10 Dispatch Table Entries 38: INT22 (Reserved) 39: INT23 (VTUD Interrupt Request 4) 40: INT24 (VTUD Interrupt Request 3) 41: INT25 (VTUD Interrupt Request 3) 42: INT26 (VTUD Interrupt Request 1) 43: INT27 (T2B Timer 2 Interrupt B) 44: ...
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INTBASE Table 11 Maskable Interrupt Priority List Interrupt Request IRQ31 RTI (Timer 0), highest priority IRQ30 T1A (Timer 1 input A) IRQ29 T1B (Timer 1 input B) IRQ28 T2A (Timer 2 input A) IRQ27 T2B (Timer 2 input B) IRQ26 ...
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Interrupt Status Register 0 (ISTAT0) — Interrupt Status Register 1 (ISTAT1) — Interrupt Debug Register (IDBG) The following CPU core registers are also used in processing interrupts: — Interrupt Stack Pointer (ISP) — Interrupt Base Register (INTBASE) 10.4.1 Non-Maskable ...
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Interrupt Status Register 1 (ISTAT1) The ISTAT1 register is a word-wide, read-only register that indicates which maskable interrupt inputs to the ICU31L (IRQ16 through IRQ31) are currently active. The register for- mat is shown below. 15 IST(31:16) IST(31:16) Interrupt ...
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Power Management The Power Management Module (PMM) improves the effi- ciency of the device by changing the operating mode (and therefore the power consumption) according to the required level of device activity. The device can operate in any of ...
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Reset Active PSM =1 Power Save IDLE =1 and WAIT HALT =1 and WAIT Idle Halt Figure 6. Power Modes and Transitions Some of the power-up transitions are based on the occur- rence of a wake-up event. An event of ...
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Active to Power Save Mode A transition from the Active mode to the Power Save mode is accomplished by writing the PMCSR.PSM bit. The transition to Power Save mode is either initiated immediately or upon execution ...
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Dual Clock and Reset The Dual Clock and Reset module (CLK2RES) generates a high-speed main system clock from an external crystal net- work and a slow clock (32.768 kHz or other rate) for operat- ing the device in Power ...
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C1 C2 Table 13 Component Values of the High Frequency Crystal Circuit Component Parameters Oscillator Resonance Frequency Type Max. Serial Resistance Max. Shunt Capacitance Load Capacitance Crystal Resistor R1 Resistor R2 Capacitor C1, C2 Table 14 Component Values of the ...
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Low Speed Clk” signal, thus indicating that the slow clock is stable. For systems that do not require a reduced power consump- tion mode, the external crystal network may be omitted for the slow clock. In ...
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Multi-Input Wake-Up The Multi-Input Wake-Up (MIWU16) module monitors its 16 input channels for a software-selectable trigger condition. Upon detection of a trigger condition, the module generates an interrupt request and if enabled, a wake-up request. A wake-up request can ...
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WUI0 WUI15 WKEDG Figure 9. Multi-Input Wake-Up Module Block Diagram The register format is shown below. 15 WKEN15-WKEN0 13.3 WAKE-UP INTERRUPT CONTROL REGISTER 1 (WKCTL1) The Wake-Up Interrupt Control Register 1 (WKICTL1) regis- ter is a word-wide read/write register that ...
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OR with the register value. Instead, just write the mask directly to the register address. The register format is shown below. 15 WKCL15-WKCL0 13.7 PROGRAMMING PROCEDURES To set up and use the Multi-Input Wake-Up function, ...
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Real-Time Timer and WATCHDOG The Timing and WATCHDOG Module (TWM) generates the clocks and interrupts used for timing periodic functions in the system, and also provides Watchdog protection against soft- ware errors. The module operates off the slow clock ...
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When the counter reaches zero, an internal timer signal called T0OUT is set to 1 for one T0IN clock cycle. This signal sets the TC bit in the TWMT0 Control and Status Register (T0CSR). It also generates an interrupt called ...
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LTWCP Lock TWCP Register. When cleared to 0, ac- cess to the TWCP register is allowed. When set to 1, the TWCP register is locked. LTWMT0 Lock TWMT0 Register. When cleared to 0, ac- cess to the TWMT0 and T0CSR ...
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Write the desired values into the TWM Clock Prescaler register (TWCP) and the TWM Timer 0 register (TWMT0) to control the T0IN and T0OUT clock rates. The frequency of T0IN can be programmed to any of six frequencies ranging ...
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Multi-Function Timer The Multi-Function Timer (MFT16) module contains two inde- pendent timer/counter units called MFT1 and MFT2, each containing a pair of 16-bit timer/counters. Each timer/counter unit offers a choice of clock sources for operation and can be configured ...
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Prescaler Register TnPRSC 5-bit Reset Prescaler Counter System Clock TnB Synchr. External Event Clock The TnB I/O pin can be configured to operate as an external event input clock for either of the two 16-bit counters. This in- put can ...
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TIMER OPERATING MODES Each timer/counter unit can be configured to operate in any of the following modes: — Processor-Independent Pulse (PWM) mode — Dual Input Capture mode — Dual Independent Timer mode — Single Input Capture and Single Timer ...
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The TnA and TnB pins function as capture inputs. A transition received on the TnA pin transfers the timer contents to the TnCRA register. Similarly, a transition received on the TnB Timer I Timer/Counter I Clock Timer II Timer/Counter II ...
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Timer I Clock Timer II Clock Clock Selector Figure 16. Timer/Counter I (TnCNT1) counts down at the rate of the se- lected clock. Upon underflow reloaded from the TnCRA register and counting proceeds down from the reloaded val- ...
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Reload A TnCRA Timer I Timer/Counter I Clock TnCNT1 Capture B TnCRB Timer II Timer/Counter II Clock TnCNT2 Figure 17. Mode 4: Input Capture Plus Timer Block Diagram counter or to operate in the pulse accumulate mode because the TnB ...
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Mode 1 Interrupt Sys. Int. pending PWM + Counter flag Timer TnAPND TnCNT1 reload from Int. I TnCRA (TnA Int.) TnBPND TnCNT1 reload from TnCRB TnCPND N/A Timer TnDPND TnCNT2 underflow Int. II (TnB Int.) Mode 1 TnAEN I/O TnBEN ...
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TIMER REGISTERS The following CPU-accessible registers are used to control the Multi-Function Timers: — Clock Prescaler Register (TnPRSC) — Clock Unit Control Register (TnCKC) — Timer/Counter I Register (TnCNT1) — Timer/Counter II Register (TnCNT2) — Reload/Capture A Register (TnCRA) ...
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TnBEN TnB Enable. When set (1), the TnB pin in en- abled to operate in Mode 2 (Dual Input Cap- ture) or Mode 4 (Single Input Capture and ...
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Versatile-Timer-Unit (VTU) The Versatile Timer Unit (VTU) contains four fully indepen- dent 16-bit timer subsystems. Each timer subsystem can op- erate either as dual 8-bit PWM timers single 16-bit PWM timer 16-bit counter with ...
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Dual 8-bit PWM Mode Each timer subsystem may be configured to generate two fully independent PWM waveforms on the respective TIOx pins. In this mode, the counter COUNTx is split and operates as two independent 8-bit counters. Each counter ...
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In that case the counter will count and then roll over TIOx pin always changes its state at the 00 tion of the counter. The user software ...
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TMOD1=11 C1PRSC == Prescaler Counter T1RUN 15 COUNT1[15:0] Restart capture PERCAP1[15:0] capture DTYCAP1[15:0] cap rst 2 0 C1EDG TIO1 Figure 22. VTU Dual 16-bit ...
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Mode Control Register (MODE) The Mode Control (MODE) registries a word-wide read/write register which controls the mode selection of all four timer subsystems. The register is cleared (0000 TMOD4 T8RUN T7RUN TMOD3 7 ...
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IxAEN bit. 0 Enable system interrupt request for the IxAPD pending flag 1 Disable system interrupt request for the IxAPD pending flag IxBEN Timer x interrupt B enable. Enable/Disable an ...
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The register may only be written if the counter is stopped i.e. if both TxRUN bits associated with a timer subsystem are cleared. The registers are cleared upon reset ...
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... MICROWIRE/SPI MICROWIRE/PLUS is a synchronous serial communications protocol, originally implemented in National Semiconductor's COPS™ and HPC™ families of microcontrollers to minimize the number of connections, and therefore the cost, of com- municating with peripherals. 5 MCS 8-Bit Master A/D I/O Lines DO MDIDO MDODI MSK The enhanced MICROWIRE interface module includes the following features: — ...
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Interrupt Request Read Data 16-bit Read Buffer Write Data 16-bit Shift Register Data In MSK Clock Prescaler + Select System Clock buffer consists of the 16-bit shifter and a buffer, called the read buffer. The 16-bit shifter loads the read ...
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MSK MSB Data Out Data In MSB MSK msb Data Out Data In msb MSKn msb Data Out Data In msb MSK goes idle again. The MSK idle state can be either high or low, depending on the MIDL bit. ...
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MSKn Data Out msb msb Data new shift process starts before MWDAT was written, i.e., while MWDAT does not contain any valid data, and the “Echo Enable” (MECH) bit is set to 1, the data received from ...
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DIN Shift Register Low-Byte (store) Read Buffer read 17.5.2 MICROWIRE Control Register (MWCTL) Upon reset, all non-reserved bits are cleared to 0. The regis- ter format is shown below MCDV ...
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In the normal mode, the output data is clocked out on the falling edge of MSK and the input data is sampled on the rising edge of MSK. In the alternate mode, the output data is clocked out ...
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USART The USART module is a full-duplex Universal Synchronous/ Asynchronous Receiver/Transmitter that supports a wide range of software-programmable baud rates and data for- mats. It handles automatic parity generation and several er- ror detection schemes. There are one or ...
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UnRBUF register. The RSFT register is not user ac- cessible. Control and Error Detection Parity Generator/Checker Sample STARTBIT Figure 33. USART ...
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CKX TDX RDX Sample Input Figure 34. USART Synchronous Communication While the TSFT is shifting out the current character on the TDXn pin, the UnTBUF register may be loaded by the soft- ware with the next byte to be transmitted. ...
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UnXB9 and UnRB9. Parity is not generated or verified in this mode. 3 START 9 BIT DATA BIT 3a START 9 BIT DATA BIT Figure ...
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The interrupts can be individually enabled or disabled using the Enable Transmit Interrupt (UnETI), Enable Receive Inter- rupt (UnERI) and Enable Receive Error Interrupt (UnEER) bits in the UnICTRL register. A transmit interrupt is generated when both the UnTBE and ...
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UnPSEL Parity Select. This 2-bit field selects parity type as follows odd parity 01 = even parity 10 = mark ( space (1) When the USART is configured to transmit nine data bits per frame, the ...
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UnETI Enable Transmitter Interrupt. This read/write bit, when set to 1, enables generation of an in- terrupt when the hardware sets the UnTBE bit. UnERI Enable Receiver Interrupt. This read/write bit, when set to 1, enables generation of an inter- ...
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ACCESS.bus Interface The ACCESS.bus interface module (ACB two wire serial interface compatible with the ACCESS.bus physical layer. It permits easy interfacing to a wide range of low-cost memo- ries and I/O devices, including: EEPROMs, SRAMs, timers, A/D ...
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Acknowledgment Signal From Receiver SDA MSB SCL ACK Start Condition Byte Complete Clock Line Held I Low ...
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Master Mode An ACCESS.bus transaction starts with a master device re- questing bus mastership. It sends a Start Condition, followed by the address of the device it wants to access. If this trans- action is successfully completed, the software ...
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For a repeated start: — Set the ACBCTL1.START bit. — In master receive mode, read the last data item from ACBSDA. — Follow the address send sequence, as described in “Sending ...
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ACB REGISTERS The ACCESS.bus Interface uses the following registers: — ACB Serial Data Register (ACBSDA) — ACB Status Register (ACBST) — ACB Status Control Register (ACBCST) — ACB Control 1 Register (ACBCTL1) — ACB Control 2 Register (ACBCTL2) — ...
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STOP condition or a one is written to it. MATCH Address Match. In slave mode, MATCH is set when ACBADDR.SAEN is set and the first sev- en bits of the address byte (the first byte trans- ...
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The clock low time and high time are defined as follows 2*SCLFRQ*t SCLl SCLh Where t is this device’s clock cycle when in CLK Active mode. SCLFRQ may be programmed ...
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CR16CAN Module The CR16CAN device contains a FULL-CAN class, CAN (Controller Area Network) serial bus interface for low/high speed applications. It supports the reception and transmis- sion of extended frames with 29-bit identifier, standard frames with 11-bit identifier, applications ...
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CAN CORE Bit Stream Processor control INTERFACE MANAGEMENT Interface Management Processor Acceptance Filtering STATUS REGISTER BTL CONFIG CAN PRESCALER CONTROL ACCEPTANCE MASKS Figure 44. www.national.com CANTX 2:1 CTX 0 1 Transceiver Logic BTL, RX shift, TX shift, CRC Error Management ...
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BASIC CAN CONCEPTS This section provides a generic overview of the basic con- cepts of the Controller Area Network (CAN). The CAN protocol is a message based protocol that allows a 11 total of 2032 ( = 2 -16) ...
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Frame Fields Data and remote frames consist of the following different bit fields: — Start of Frame — Arbitration Field — Control Field — Data Field ...
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STANDARD DATA FRAME (number of bits = 44 + 8N) Arbitration Field Control Field IDENTIFIER DATA 10 ... 0 LENGTH CODE Bit Stuffing EXTENDED DATA FRAME (number of bits = 64 + 8N) ...
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STANDARD REMOTE FRAME (number of bits = 44) Arbitration Field Control Field IDENTIFIER 10 ... 0 EXTENDED REMOTE FRAME (number of bits = 64) Arbitration Field IDENTIFIER 28 ... 18 Note: ...
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Error Frame As shown in Figure48, the Error Frame consists of the error flag and the error delimiter bit fields. The error flag field is built up from the various error flags of the different nodes. Therefore, its length may ...
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Interframe Space Data and remote frames are separated from every preceding frame (data, remote, error and overload frames) by the inter- frame space (see Figure50). Error and overload frames are ANY FRAME INT ...
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Synchronize Once the CR16CAN is enabled, it goes into a synchro- nization state to synchronize with the bus by waiting for 11 consecutive recessive bits. After that the CR16CAN becomes error active and can participate in the bus communication. ...
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If only one device is on the bus and this device trans- mits a message, it will get no acknowledgment. This will be detected as an error and the message will be re- peated. When the device goes ‘error ...
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BUS SIGNAL PREVIOUS A BIT PREVIOUS A BIT PREVIOUS A BIT PREVIOUS A BIT 20.2.4 Clock Generator The CAN prescaler (PSC) is shown is Figure55. It divides the CKI input clock by the value defined in the CTIM register. ...
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A dedicated acceptance filtering procedure enables the user to configure each buffer to receive only a single message group of messages. One buffer uses an independent fil- tering procedure, which provides the possibility to establish a BASIC-CAN ...
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Note: If the BMASK register is equal to the GMASK register, the buffer 14 can be used the same way as the buffers 0 to 13. The buffers are scanned prior to buffer 14. Subse- quently, the ...
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CR16CAN HIDDEN RECEIVE BUFFER Figure 60. Receive Buffer Structure The received data frame will be stored in the first matching receive buffer beginning with buffer 0. For example, if the message is accepted by buffer 5, then at the time ...
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If the status is changed during BUSY being active, the status is updated by the CR16CAN as shown in Table21. The buffer states are indicated and controlled by the ST[3:0] bits in the CNSTAT register (see Buffer Status/Control Reg- ister ...
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RX_FULL state (see also Interrupts on page 104). In that case the procedure described below should be followed. 2. Read the status to determine if a new message has overwritten the one ...
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BUSY status. In order to cancel the transmit request of the next frame, the CPU has to change the buffer state to TX_NOT_ACTIVE. When the transmit re- quest has been overwritten by another request of a ...
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Transmit Procedure The transmission of a CAN message has to be executed as follows (see also Figure65) 1. Configure CNSTAT status field as TX_NOT_ACTIVE. If the status is TX_BUSY, a previous transmit request is still pending and the user ...
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TX Buffer States The transmission process can be started after the user has loaded the buffer registers (data, ID, DLC, PRI) and set the buffer status from TX_NOT_ACTIVE to TX_ONCE, TX_RTR or TX_ONCE_RTR. When the CPU writes TX_ONCE, the ...
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INTERRUPTS CR16CAN has access to one interrupt vector in the CR16 CPU. The interrupt process can be initiated from the follow- ing sources. • CAN data transfer — Reception of a valid data frame in the buffer. (Buffer state ...
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Usage Hints The interrupt code IST[3:0] can be used within the interrupt handler as a displacement in order to jump to the relevant subroutine. The CAN Interrupt Code Enable (CICEN) register is used in the CAN interrupt handler if ...
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Buffer Status/Control Register (CNSTAT) The buffer status, the buffer priority and the data length code are controlled by manipulating the contents of the Buffer Sta- tus/Control Register (CNSTAT). CPU and CR16CAN have access to this register. Table 26 Buffer ...
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PRI[3:0] Transmit Priority Code. The PRI[3:0] bits con- tain the user defined transmit priority code for the message buffer. DLC[3:0] Data Length Code. The DLC[3:0] bits deter- mine the number of data bytes within a re- ceived/transmitted frame. For transmission, ...
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Storage of Messages with Less Than 8 Data Bytes The data bytes that are not used for data transfer are “don’t cares”. If the message is transmitted, the data within these bytes will be ignored. If the message is ...
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Storage of Remote Messages During remote frame transfer, the buffer registers DATA[3:0] are “don’t cares” remote frame is transmitted, the con- tents of these registers are ignored remote frame is re- BUFFER ADDR 15 14 ...
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CRX Control Receive. This bit configures the logic level of the CAN receive pin CANRX. “0” dominate state is “0”; recessive state is “1” “1” dominate state is “1”; recessive state ...
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Setting the DDIR bit to “1” will cause the direction of the data storage to be reversed — the last byte received is stored at Sequence of Data Bytes on the Bus ID Data1 Data2 Storage of Data Bytes in ...
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CAN Timing Register (CTIM) The Can Timing Register (CTIM) defines the configuration of the Bit Time Logic (BTL PSC[6:0] SJW[1:0] TSEG1[3:0] TSEG2[2:0] 0 r/w PSC[6:0] Prescaler Configuration. These bits set the CAN prescaler. The ...
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GM[28:15] The following are the bits for the GMSKB reg- ister GM[28:18] RTR IDE 0 r/w GM[14:0] The following are the bits for the GMSKX reg- ister. 15 GM[14:0] 0 r/w For all GMSKB and GMSKX ...
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CAN Interrupt Pending Register (CIPND) The CIPND register indicates any CAN Receive/Transmit In- terrupt Requests caused by the message buffers 0..14 and CAN error occurrences EIPND IPND[14: EIPND Error Interrupt Pending — EIPND indicates the ...
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Table 36 Highest Priority Interrupt Code (CICEN = FFFF) CAN interrupt IRQ IST3 IST2 request Buffer Buffer Buffer Buffer Buffer 20.9.17 CAN Error Counter Register ...
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ACK and during an active error flag. 20.9.19 CAN Timer Register (CTMR) The current value of the Time Stamp counter as described in section 20.8 can be monitored via the CAN Timer ...
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The critical path derives from receiving a remote frame which triggers the transmission of one or more data frames. There are a minimum of four bit times in-between two consecutive frames. These bit times start at the validation point of ...
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Analog Comparators The Dual Analog Comparator (ACMP2) module contains two independent analog comparators with all necessary control logic. Each comparator unit compares the analog input volt- ages applied to two input pins and determines which voltage is higher. The ...
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A/D Converter The A/D Converter (ADC) module is a 12-channel, multi- plexed-input, analog-to-digital converter. The A/D Converter receives an analog voltage on an input pin and converts that voltage into an 8-bit digital value using successive approxi- mation. The ...
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CH0 CH1 CH2 CH3 CH4 CH5 12:1 SAMPLE CH6 ANALOG CH7 MUX HOLD CH8 CH9 CH10 CH11 with ADDATA3. After it loads all four registers, it clears the START bit and sets the EOC (end of conversion) bit. If the ...
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This register is initialized to 11 when a new conversion is started (when ADCCNT2.START is changed from and is automatically in- cremented every time a result is written to buff- ers ADDATA0-ADDATA3. The result is a four- ...
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A/D Converter clock cycle 001 = 2 A/D Converter clock cycles 010 = 4 A/D Converter clock cycles 011 = 8 A/D Converter clock cycles 100 = 16 A/D Converter clock cycles 101 = 32 A/D Converter ...
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Memory Map The CompactRISC architecture supports a uniform linear ad- dress space of 2 megabytes. The device implementation of this architecture uses only the lowest 128K bytes of address space, ranging from 0000 to 1FFFF hex. Table42 is a ...
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Register Register Name Size Address 32K/48K 3K 2K 1.5K 128 CMB0_CNTSTAT word CMB0_TSTP word CMB0_DATA3 word CMB0_DATA2 word CMB0_DATA1 word CMB0_DATA0 word CMB0_ID0 word CMB0_ID1 word CMB1 8-word CMB2 8-word CMB3 8-word CMB4 8-word CMB5 8-word CMB6 8-word CMB7 8-word ...
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Table 43 Device Detailed Memory Map Register Register Name Size Address (hex) FLCTRL1 byte F930 FLSEC byte F932 ISPKEY byte F934 FLCTRL2 word F936 DMCSR byte F940 DMPSLR byte F942 DMSTART byte F944 DMTRAN byte F946 DMPROG byte F948 DMERASE ...
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Register Register Name Size Address PGDIR byte PGDIN byte PGDOUT byte PGWKPU byte PHALT byte PHDIR byte PHDIN byte PHDOUT byte PHWKUP byte PFALT byte PFDIR byte PFDIN byte PFDOUT byte PFWKPU byte IVCT byte NMISTAT byte EXNMI byte ISTAT0 ...
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Table 43 Device Detailed Memory Map Register Register Name Size Address (hex) ACBCST byte FEC4 ACBCTL1 byte FEC6 ACBADDR byte FEC8 ACBCTL2 byte FECA PIALT byte FEE0 PIDIR byte FEE2 PIDIN byte FEE4 PIDOUT byte FEE6 PIWKPU byte FEE8 PLALT ...
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Register Register Name Size Address PERCAP1 word DTYCAP1 word COUNT2 word PERCAP2 word DTYCAP2 word CLK2PS word COUNT3 word PERCAP3 word DTYCAP3 word COUNT4 word PERCAP4 word DTYCAP4 word ADCST byte ADCCNT1 byte ADCCNT2 byte ADCCNT3 byte ADDATA0 byte ADDATA1 ...
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Register Layouts The following tables show the functions of the bit fields of the device registers. For more information on using these registers, see the detailed description of the applicable function elsewhere in this data sheet. 24.1 REGISTER LAYOUT ...
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MCFG Reserved MSTAT BIU Registers 15 12 BCFG IOCFG Reserved SZCFG0 Reserved SZCFG1 Reserved ISP Registers FLCTRL1 Reserved FLCTRL2 EMPTY Reserved FLSEC Reserved ISPKEY Reserved Flash Data Memory Registers DMCSR DMPSLR Reserved ...
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FLPROG FLERASE FLEND FLPCNT FLCNT1 FLCNT2 PGMKEY GPIO Registers PxALT PxDIR PxDIN PxDOUT PxWPU ICU31L Registers IVCT Reserved NMISTAT EXNMI ISTAT0 ISTAT1 IENAM0 IENAM1 IDBG Reserved MIWU16 Registers WKEDG WKENA WKICTL1 WKINTR7 WKINTR6 ...
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Dual Clock + Reset Registers CRCTRL PRSSC PRSSC1 Power Management Register PMCSR USART Registers 7 UnTBUF UnRBUF UnICTRL UnEEI UnSTAT Reserved UnFRS Reserved UnMDSL UnBAUD UnPSR MWSPI16 15 9 Registers MWDAT MWCTL MCDV MIDL MWSTAT www.national.com ...
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ACB Registers 7 ACBSDA ACBST SLVSTP SDAST ACBCST Reserved ACBCTL1 STASTRE NMINTE ACBADDR SAEN ACBCTL2 TIMER Registers TnCNT1 TnCRA TnCRB TnCNT2 TnPRSC TnCKC TnCTRL Reserved TnAOUT TnICTL TnDIEN TnICLR DATA BER NEGACK STASTR TGSCL ...
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VTU Registers MODE TMOD4 T8RUN T7RUN IO1CTL P4POL C4EDG IO2CTL P8POL C8EDG INTCTL I4DEN I4CEN I4BEN I4AEN INTPND I4DPD I4CPD I4BPD I4APD CLK1PS C2PRSC COUNT1 PERCAP1 DTYCAP1 COUNT2 PERCAP2 DTYCAP2 CLK2PS C4PRSC COUNT3 PERCAP3 DTYCAP3 COUNT4 ...
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A/D Registers 7 ADCST Reserved ADCCNT1 ADCCNT2 START ADCCNT3 Reserved ADDATA0 ADDATA1 ADDATA2 ADDATA3 Analog Comp. Registers 7 6 CMPCTRL Reserved BUFPTR Reserved Reserved Reserved SCAN CONT PWREN DELAY RESULT 1 DATA RESULT 2 DATA RESULT 3 ...
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... ELECTRICAL AND THERMAL CHARACTERISTICS Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage ( Voltage at Any Pin * ESD Protection Level Total Current into V Pin (Source) CC Thermal Characteristics Characteristics Average junction temperature ...
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Symbol Parameter I SDA, SCL Logical 0 CMOS Output Current OLACB I Weak Pull-up Current OHW I RESET pin Weak Pull-down Current IL I High Impedance Input Leakage Current L I (Off) Output Leakage Current O (I/O pins in input ...
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The input signal is measured across the internal capacitance. f. Conversion result never decreases with an increase in input voltage and has no missing codes. www.national.com 138 ...
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Analog Comparator Characteristics Symbol Parameter V Input Offset Voltage Input Common Mode Voltage Range Supply Current per Comparator (When CS Enabled) Response Time Flash EEPROM Program Memory Programming Symbol Parameter t Programming pulse width ...
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Flash EEPROM Data Programming Symbol Parameter a re-programming time t Programming pulse width PWD c t Erase pulse width EWD t Charge pump power-up time SDD t Program/erase transition time TTD t Charge pump enable hold time PED t Charge ...
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Row Select/ Start Charge Pump Select Charge Pump/ Enable Programming Voltage Programming Pulse t SD Figure 76. Flash EEPROM Memory Programming Timing (Sample Sequence for Programming two Words into Flash EEPROM Program Memory Output Signal Levels All output signals are ...
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Timing Waveforms X1 X2 CLK Output Valid Output Signal Input Signal Control Signal 1 Control Signal 2 www.national.com t X1p t t X1h X1l t X2p t t X2h X2l t CLKp t t CLKr CLKf t t CLKh ...
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CLK ISE NMI Figure 78. ISE & NMI Signal Timing CLK RESET Figure 79. Non-Power-On Reset CLK t COv1 TXDn t IS RXDn t IH Figure 80. USART Asynchronous Mode ...
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CLK PORTS B, C (input) PORTS B, C (output) BUZCLK MSKn t MSKs msb Data In t MDIs MDIDOn msb (slave) t MDOf MDODIn msb (master) t MSKd MCSn (Slave) t MCSs Figure 83. MICROWIRE Transaction Timing, Normal Mode, MIDL ...
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MSKn t t MSKs MSKl Data In t MDIDOn (slave) t MDOf MDODIn msb (master) MCSn (Slave) t MCSs Figure 84. MICROWIRE Transaction Timing, Normal Mode, MIDL bit = 1 t MSKp MSKn t MSKs t MSKh Data In t ...
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MSKn t MSKs Data In t MDIs MDIDOn (Slave) t MDOf MDODIn (Master) t SKd MCSn (Slave only) t MCSs Figure 86. MICROWIRE Transaction Timing, Alternate Mode, MIDL bit = 1 MSKn t t MSKs MSKh DI msb MDODIn (Slave) ...
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SDA CC 0.3V CC 0.7V CC SCL 0.3V CC Note: In the timing tables the parameter name is added with an “o” for output signal timing and “i” for input signal timing. Figure 88. ACB signals (SDA and SCL) ...
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CLK TIOx CLK TIOx www.national.com Figure 91. ACB Data Bits Timing t t TIOL TIOH Figure 92. Versatile-Timer-Unit Input Timing t t TIOL TIOH Figure 93. Versatile-Timer-Unit Input Timing 148 ...
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Timing Tables Symbol Figure Description a Tclk 77 CLK clock period CLK high time t 77 CLKh CLK low time t 77 CLKl t 77 CLK rise time on R.E. CLK CLKr t 77 CLK fall time on F.E. ...
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Symbol Figure Description t 88 SCL signal Rise time SCLro t 91 SCL low time SCLlowo t 91 SCL high time SCLhigho t SDA signal Fall time 88 SDAfo t SDA signal Rise time 88 SDAro t 91 SDA hold ...
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Symbol Figure Description 83 MICROWIRE Clock Period t MSKp MSK Hold (slave only) MSKh t 83 MSK Setup (slave only) MSKs 83 MCS Hold (slave only) t MCSh 84 83 MCS Setup (slave only) t MCSs 84 ...
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Appendix The following document describes problems identified in the CR16 modules. 26.1 CR16CAN 26.1.1 CR16CAN Problem Descriptions: Under certain conditions it occurs that the CR16CAN module receives a frame, sent by itself even though the loopback fea- ture is ...
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Message sent from another CAN node received into buffer 1. Buffer 1 and buffer 2 are tagged for reception of this message. 2. Message sent from another CAN node received into buffer 3 (ID=0x15555003). Only buffer 3 is now ...
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When a frame was successfully sent by CR16CAN the con- tents of the Time Stamp counter are captured into the Time Stamp register (TSTP) of the transmit buffer during the ACK- slot of the frame currently being sent. Also, when ...
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Every time the user (CR16B core) writes to a TWM configu- ration register or to the WATCHDOG Service Data Match register, this “high speed operation” must be synchronized to the internal TWM logic running at the slow clock rate. This ...
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... NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, ...