CR16MCS9VJE8 National Semiconductor, CR16MCS9VJE8 Datasheet - Page 46

• Manufacturer Part Number: CR16MCS9VJE8
• Description: 16-Bit Microcontroller IC
• Manufacturer: National Semiconductor

Specifications of CR16MCS9VJE8

• Controller Family/series: CR16X
• Core Size: 16 Bit
• Program Memory Size: 64K X 8 Flash
• Digital Ic Case Style: PQFP
• No. Of Pins: 80
• Mounting Type: Surface Mount
• Clock Frequency: 25MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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When the counter reaches zero, an internal timer signal
called T0OUT is set to 1 for one T0IN clock cycle. This signal
sets the TC bit in the TWMT0 Control and Status Register
(T0CSR). It also generates an interrupt called RTI (IRQ14) if
the interrupt is enabled by the T0CSR.T0INTE bit.
If the software loads TWMT0 with a new value, the timer uses
that value the next time that it reloads the 16-bit timer register
(in other words, after reaching zero). The software can restart
the timer at any time (on the very next edge of the T0IN clock)
by setting the Restart (RST) bit in the T0CSR register. The
T0CSR.RST bit is cleared automatically upon restart of the
16-bit timer.
Note: If the user wishes to switch to power save or idle mode
after setting T0CSR.RST, the user must wait for reset opera-
tion to complete before doing the switch.
14.3
The WATCHDOG is an 8-bit down counter that operates on
the rising edge of a specified clock source. Upon reset, the
WATCHDOG is disabled; it does not count and no WATCH-
DOG signal is generated. A write to either the WATCHDOG
Count (WDCNT) register or the WATCHDOG Service Data
Match (WDSDM) register starts the counter. The WATCH-
DOG counter counts down from the value programmed in to
the WDCNT register. Once started, only a reset can stop the
WATCHDOG from operating.
The WATCHDOG can be programmed to use either T0OUT
or T0IN as its clock source (the output and input of Timer T0,
respectively). The TWCFG.WDCT0I bit controls this clock
selection.
The software must periodically “service” the WATCHDOG.
There are two ways to service the WATCHDOG, the choice
depending on the programmed value of the WDSDME bit in
the Timer and WATCHDOG Configuration (TWCFG) register.
If TWCFG.WDSDME bit is cleared to 0, the WATCHDOG is
serviced by writing a value to the WDCNT register. The value
written to the register is reloaded into the WATCHDOG
counter. The counter then continues counting down from that
value.
If TWCFG.WDSDME bit is set to 1, the WATCHDOG is ser-
viced by writing the value 5C hex to the WATCHDOG Service
Data Match (WDSDM) register. This reloads the WATCH-
DOG counter with the value previously programmed into the
WDCNT register. The counter then continues counting down
from that value.
A WATCHDOG error signal is generated by any of the follow-
ing events:
A WATCHDOG error condition resets the device.
14.3.1
The Timer and WATCHDOG Configuration (TWCFG) regis-
ter is used to set the WATCHDOG configuration. It controls
the WATCHDOG clock source (T0IN or T0OUT), the type of
WATCHDOG servicing (using WDCNT or WDSDM), and the
— The WATCHDOG serviced too late.
— The WATCHDOG serviced too often.
— The WDSDM register is written with a value other than
5C hex when WDSDM type servicing is enabled
(TWCFG.WDSDME=1).
Register Locking
WATCHDOG OPERATION
46
locking state of the TWCFG, TWCPR, TIMER0, T0CSR, and
WDCNT registers. A register that is locked cannot be read or
written. A write operation is ignored and a read operation re-
turns unpredictable results.
If the TWCFG register is itself locked, it remains locked until
the device is reset. Any other locked registers also remain
locked until the device is reset. This feature prevents a run-
away program from tampering with the programmed
WATCHDOG function.
14.3.2
The Timer and WATCHDOG Module is active in both the
Power Save and Idle modes. The clocks and counters con-
tinue to operate normally in these modes. The WDSDM reg-
ister is accessible in the Power Save and Idle modes, but the
other TWM registers are accessible only in the Active mode.
Therefore, WATCHDOG servicing must be carried out using
the WDSDM register in the Power Save or Idle mode.
In the Halt mode, the entire device is frozen, including the
Timer and WATCHDOG Module. Upon return to the Active
mode, operation of the module resumes at the point at which
it was stopped.
Note: After a restart or WATCHDOG service through WD-
CNT, do not enter Power Save mode for a period equivalent
to 5 slow clock cycles.
14.4
The TWM registers controls the operation of the Timing and
WATCHDOG Module. There are six such registers:
The WDSDM register is accessible in both Active and Power
Save mode. The other TWM registers are accessible only in
Active mode.
14.4.1
The TWCFG register is a byte-wide, read/write register that
selects the WATCHDOG clock input and service method,
and also allows the WATCHDOG registers to be selectively
locked. Once a bit is set, that bit cannot be cleared until the
device resets. Upon reset, the non-reserved bits of the regis-
ter are all cleared to 0. The register format is shown below.
LTWCFG
Reserved WDSDME WDCT0I LWDCNT LTWMT0 LTWCP LTWCFG
7
— Timer
— Timer and WATCHDOG Clock Prescaler Register
— TWM Timer 0 Register (TWMT0)
— TWMT0 Control and Status Register (T0CSR)
— WATCHDOG Count Register (WDCNT)
— WATCHDOG Service Data Match Register (WDSDM)
(TWCFG)
(TWCP)
6
Power Save Mode Operation
TWM REGISTERS
Timer and WATCHDOG Configuration Register
(TWCFG)
5
Lock TWCFG Register. When cleared to 0, ac-
cess to the TWCFG register is allowed. When
set to 1, the TWCFG register is locked. A
locked register cannot be read or written; a
read operation returns unpredictable values
and a write operation is ignored. Locking the
TWCFG register remains in effect until the de-
vice is reset.
and
WATCHDOG
4
3
Configuration
2
1
Register
0