CR16MCS9VJE8 National Semiconductor, CR16MCS9VJE8 Datasheet - Page 114

• Manufacturer Part Number: CR16MCS9VJE8
• Description: 16-Bit Microcontroller IC
• Manufacturer: National Semiconductor

Specifications of CR16MCS9VJE8

• Controller Family/series: CR16X
• Core Size: 16 Bit
• Program Memory Size: 64K X 8 Flash
• Digital Ic Case Style: PQFP
• No. Of Pins: 80
• Mounting Type: Surface Mount
• Clock Frequency: 25MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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20.9.13 CAN Interrupt Pending Register (CIPND)
The CIPND register indicates any CAN Receive/Transmit In-
terrupt Requests caused by the message buffers 0..14 and
CAN error occurrences.
EIPND
IPND[14:0]
20.9.14 CAN Interrupt Clear Register (CICLR)
The bits in the CICLR register separately clear all CAN inter-
rupt pending flags caused by the message buffers 0...14 and
from the Error Management Logic.
EICLR
ICLR[14:0]
20.9.15 CAN Interrupt Code Enable Register (CICEN)
The CAN Interrupt Code Enable Register (CICEN) deter-
mines whether the interrupt pending flag in IPND should be
translated into the Interrupt Code field of the CSTPND regis-
ter. All interrupt requests, CAN error and buffer 0...14 inter-
rupts can be enabled/disabled separately for the interrupt
code indication field.
EICLR
EIPND
15
15
EICEN
14
14
15
Error Interrupt Pending — EIPND indicates the
status change of TEC/REC and will execute an
error interrupt if EIEN is set. The user has the
responsibility to reset EIPND by means of the
CICLR register.
“0” CAN status is not changed
“1” CAN status is changed
Buffer Interrupt Pending — IPND[14:0] bits are
set by CR16CAN following a successful trans-
mission or reception of a message to or from
message buffer 0...14, IPND14 for buffer 14
and IPND0 for buffer 0.
“0” no interrupt pending for this message buff-
“1” message buffer has generated an inter-
Error Interrupt Clear. The EICLR bit can clear
the EIPND bit:
“0” the contents of the EIPND bit is un-
“1” the contents of the EIPND bit is reset
Buffer Interrupt Clear. The user is able to clear
the buffer interrupt pending bits by ICLR[14:0]:
“0” the contents of the respective IPND bit is
“1” the contents of the respective IPND bit is
er
rupt
changed
unchanged
reset
14
r/w
ICLR[14:0]
IPND[14:0]
w
0
0
0
r
ICEN[14:0]
0
0
0
114
EICEN
ICEN[14:0]
20.9.16 CAN Status Pending Register (CSTPND)
The CAN Status Pending Register (CSTPND) contains the
status of the CAN Node and the Interrupt Code.
NS[2:0]
IRQ,IST[3:0] Interrupt Code. This section of the Status
Table 36
CAN interrupt
15
Error interrupt
NS2
no request
0
0
0
1
1
request
Buffer 0
Buffer 1
Buffer 2
Buffer 3
Buffer 4
Buffer 5
Buffer 6
Buffer 7
Buffer 8
Buffer 9
Reserved
Highest Priority Interrupt Code
(CICEN = FFFF)
Error Interrupt Code Enable:
“0” error interrupt pending is not indicated in
“1” error interrupt pending is indicated in the
Buffer Interrupt Code Enable:
“0” buffer interrupt pending is not indicated in
“1” buffer interrupt pending is indicated in the
CAN Node Status. This bits indicate the status
of the CAN node as it is described in Table35.
Pending Register represents the interrupt
source of the highest priority interrupt currently
pending and enabled in the CICEN register.
Table36 shows the several interrupt codes for
CICEN=FFFF.
NS1
Table 35 CAN Node Status
0
1
1
0
1
the interrupt code
interrupt code
the interrupt code
interrupt code
8
IRQ
0
1
1
1
1
1
1
1
1
1
1
1
7
NS0
NS[2:0]
X
X
0
0
1
IST3
0
r
0
0
0
0
0
0
0
0
0
1
1
1
5
Error Warning Level
IRQ
IST2
4
0
0
0
0
0
1
1
1
1
0
0
0
Error passive
Node Status
Error active
Not Active
Bus off
IST1
3
0
0
0
1
1
0
0
1
1
0
0
1
IST[3:0]
IST0
0
0
1
0
1
0
1
0
1
0
1
0
0