CR16MCS9VJE8 National Semiconductor, CR16MCS9VJE8 Datasheet - Page 99

16-Bit Microcontroller IC

CR16MCS9VJE8

Manufacturer Part Number
CR16MCS9VJE8
Description
16-Bit Microcontroller IC
Manufacturer
National Semiconductor
Datasheet

Specifications of CR16MCS9VJE8

Controller Family/series
CR16X
Core Size
16 Bit
Program Memory Size
64K X 8 Flash
Digital Ic Case Style
PQFP
No. Of Pins
80
Mounting Type
Surface Mount
Clock Frequency
25MHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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If the status is changed during BUSY being active, the status
is updated by the CR16CAN as shown in Table21.
The buffer states are indicated and controlled by the ST[3:0]
bits in the CNSTAT register (see Buffer Status/Control Reg-
ister (CNSTAT) on page 106. The various receive buffer
states are explained in RX Buffer States on page 100.
20.5.2
The user has to execute the following procedure to initialize
a message buffer for the reception of a CAN message.
In order to read the out of a received message, the CPU has
to execute the following steps (see Figure62):
1. Configure the receive masks (GMASK or BMASK, re-
2. Configure the buffer ID.
3. Configure the message buffer status as RX_READY.
spectively).
Receive Procedure
99
The first step is only applicable if polling is used to get the
status of the receive buffer. It can be deleted for an interrupt
driven receive routine.
1. Read the status (CNSTAT) of the receive buffer. If the
Figure 62. Buffer Read Routine (BUFFLOCK Disabled)
status is RX_READY, no was the message received, ex-
it. If the status is RX_BUSY, copy process from hidden
receive buffer is not completed yet, read CNSTAT again.
If a buffer is configured to RX_READY and its interrupt
is enabled, it will generate an interrupt as soon as the
Y
read buffer (id/data/cntrl)
Interrupt Entry Point
write RX_READY
RX_OVERRUN?
RX_OVERRUN?
clear RX_PND
read CNSTAT
RX_BUSYx?
read CNSTAT
RX_READY?
RX_FULL? or
RX_BUSYx?
read buffer
N
N
N
N
exit
Y
Y
Y
(optional, for information)
reading data from the
receive buffer
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