CR16MCS9VJE8 National Semiconductor, CR16MCS9VJE8 Datasheet - Page 53

• Manufacturer Part Number: CR16MCS9VJE8
• Description: 16-Bit Microcontroller IC
• Manufacturer: National Semiconductor

Specifications of CR16MCS9VJE8

• Controller Family/series: CR16X
• Core Size: 16 Bit
• Program Memory Size: 64K X 8 Flash
• Digital Ic Case Style: PQFP
• No. Of Pins: 80
• Mounting Type: Surface Mount
• Clock Frequency: 25MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Timer/Counter I (TnCNT1) counts down at the rate of the se-
lected clock. Upon underflow, it is reloaded from the TnCRA
register and counting proceeds down from the reloaded val-
ue. In addition, the TnA pin is toggled on each underflow if
this function is enabled by the TnAEN bit. The initial state of
the TnA pin is software-programmable. When the TnA pin is
toggled from low to high, it sets the TnCPND interrupt pend-
ing flag and also generates an interrupt if the interrupt is en-
abled by the TnAIEN bit.
Because TnA toggles on every underflow, a 50% duty cycle
PWM signal can be generated on TnA without any further ac-
tion from the CPU once the pulse train is initiated.
Timer/Counter II (TnCNT2) counts down at the rate of the se-
lected clock. Upon underflow, it is reloaded from the TnCRB
register and counting proceeds down from the reloaded val-
ue. In addition, each underflow sets the TnDPND interrupt
pending flag and generates an interrupt if the interrupt is en-
abled by the TnDIEN bit.
15.2.4
Mode 4 is the Single Input Capture and Single Timer mode,
which provides one external event counter and one system
timer.
Figure17 is a block diagram of the Multi-Function Timer con-
figured to operate in Mode 4. This mode offers a combination
of Mode 3 and Mode 2 functions. Timer/Counter I is used as
a system timer as in Mode 3 and Timer/Counter II is used as
a capture timer as in Mode 2, but with a single input rather
than two inputs.
Mode 4: Input Capture Plus Timer
Timer I
Timer II
Selector
Clock
Clock
Clock
Figure 16.
Mode 3: Dual Independent Timer/Counter Block Diagram
Timer/Counter I
Timer/Counter II
TnCNT1
Reload A
Reload B
TnCRA
TnCRB
TnCNT2
Underflow
Underflow
53
Timer/Counter I (TnCNT1) operates the same as in Mode 3.
It counts down at the rate of the selected clock. Upon under-
flow, it is reloaded from the TnCRA register and counting pro-
ceeds down from the reloaded value. The TnA pin is toggled
on each underflow if this function is enabled by the TnAEN
bit. When the TnA pin is toggled from low to high, it sets the
TnCPND interrupt pending flag and also generates an inter-
rupt if the interrupt is enabled by the TnAIEN bit. A 50% duty
cycle PWM signal can be generated on TnA without any fur-
ther action from the CPU once the pulse train is initiated.
Timer/Counter II (TnCNT1) counts down at the rate of the se-
lected clock. The TnB pin functions as the capture input. A
transition received on TnB transfers the timer contents to the
TnCRB register. The input pin can be configured to sense ei-
ther rising or falling edges.
The TnB input can be configured to preset the counter to
FFFF hex upon reception of a valid capture event. In this
case, the current value of the counter is transferred to the
capture register and then the counter is preset to FFFF hex.
The values captured in the TnCRB register at different times
reflect the elapsed time between transitions on the TnA pin.
The input signal on TnB must have a pulse width equal to or
greater than one system clock cycle.
There are two separate interrupts associated with the cap-
ture timer, each with its own enable bit and pending flag. The
two interrupt events are reception of a transition on TnB and
underflow of the TnCNT2 counter. The enable bits for these
events are TnBIEN and TnDIEN, respectively.
Neither Timer/Counter I (TnCNT1) nor Timer/Counter II
(TnCNT2) can be configured to operate as an external event
TnDPND
TnAPND
TnDIEN
TnAIEN
TnAEN
Interrupt II
Interrupt I
Timer
Timer
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TnA
TnB