CR16MCS9VJE8 National Semiconductor, CR16MCS9VJE8 Datasheet - Page 81

• Manufacturer Part Number: CR16MCS9VJE8
• Description: 16-Bit Microcontroller IC
• Manufacturer: National Semiconductor

Specifications of CR16MCS9VJE8

• Controller Family/series: CR16X
• Core Size: 16 Bit
• Program Memory Size: 64K X 8 Flash
• Digital Ic Case Style: PQFP
• No. Of Pins: 80
• Mounting Type: Surface Mount
• Clock Frequency: 25MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

empty buffer (ACBST.SDAST=1) and/or a stop after start
(ACBST.STASTR=1).
For a repeated start:
Master Error Detections
The ACB detects illegal Start or Stop Conditions (i.e., a Start
or Stop Condition within the data transfer, or the acknowl-
edge cycle) and a conflict on the data lines of the AC-
CESS.bus. If an illegal action is detected, BER is set, and the
MASTER mode is exited (MASTER is cleared).
Bus Idle Error Recovery
When a request to become the active bus master or a restart
operation fails, the ACBST.BER bit is set to indicate the error.
In some cases, both this device and the other device may
identify the failure and leave the bus idle. In this case, the
start sequence may not be completed and the ACCESS.bus
may remain deadlocked forever.
To recover from deadlock, use the following sequence:
19.2.2
A slave device waits in Idle mode for a master to initiate a bus
transaction. Whenever the ACB is enabled, and it is not act-
ing as a master (i.e., ACBST.MASTER is cleared), it acts as
a slave device.
Once a Start Condition on the bus is detected, this device
checks whether the address sent by the current master
matches either:
This match is checked even when ACBST.MASTER is set. If
a bus conflict (on SDA or SCL) is detected, ACBST.BER is
set, ACBST.MASTER is cleared and this device continues to
search the received message for a match.
If an address match, or a global match, is detected:
1. Clear the ACBST.BER bit and ACBCST.BB bit.
2. Wait for a time-out period to check that there is no other
3. Disable, and re-enable the ACB to put it in the non-ad-
4. At this point some of the slaves may not identify the bus
— Set the ACBCTL1.START bit.
— In master receive mode, read the last data item from
— Follow the address send sequence, as described in
— If the ACB was awaiting handling due to ACBST.STAS-
— The ACBADDR.ADDR value if ACBADDR.SAEN is
— The general call address if ACBCTL1.GCM is set.
— This device asserts its data pin during the acknowl-
— The ACBCST.MATCH and ACBST.NMATCH bits are
active master on the bus (i.e., ACBCST.BB remains
cleared).
dressed slave mode.
error. To recover, the ACB becomes the bus master by
issuing a Start Condition and sends an address field;
then issue a Stop Condition to synchronize all the
slaves.
ACBSDA.
“Sending the Address Byte” on page 80.
TR=1, clear it only after writing the requested address
and direction to ACBSDA.
set.
edge cycle.
set. If ACBST.XMIT is set (i.e., slave transmit mode),
Slave Mode
81
Slave Receive and Transmit
Slave Receive and Transmit are performed after a match is
detected and the data transfer direction is identified. After a
byte transfer the ACB extend the acknowledge clock until the
software reads or writes the ACBSDA register. The receive
and transmit sequence are identical to those used in the
master routine.
Slave Bus Stall
When operating as a slave, this device stalls the AC-
CESS.bus by extending the first clock cycle of a transaction
in the following cases:
Slave Error Detections
The ACB detects illegal Start and Stop Conditions on the AC-
CESS.bus (i.e., a Start or Stop Condition within the data
transfer or the acknowledge cycle). When an illegal Start or
Stop Condition is detected, the BER bit is set and MATCH
and GMATCH are cleared, setting the module to be an unad-
dressed slave.
Power Down
When this device is in Power Save, Idle, or Halt mode, the
ACB module is not active but retains its status. If the ACB is
enabled (ACBCTL2.ENABLE=1) on detection of a Start Con-
dition, a wake-up signal is issued to the MIWU module. Use
this signal to switch this device to Active mode.
The ACB module cannot check the address byte following
the start condition that has awaken this device for a match.
The ACB responds with a negative acknowledge, and the de-
vice should re-send both the Start Condition and the address
after this device has had time to wake up.
Check that the ACBCST.BUSY bit is inactive before entering
Power Save, Idle or Halt mode. This guarantees that this de-
vice does not acknowledge an address sent, and stop re-
sponding later.
19.2.3
The SDA and SCL are open-drain signals. For more informa-
tion, see the I/O configuration section.
19.2.4
The ACB module permits the user to set the clock frequency
used for the ACCESS.bus clock. The clock is set by the
ACBCTL2.SCLFRQ field. This field determines the SCL
clock period used by this device. This clock low period may
be extended by stall periods initiated by the ACB module or
by another ACCESS.bus device. In case of a conflict with an-
other bus master, a shorter clock high period may be forced
by the other bus master until the conflict is resolved.
— If ACBCTL1.INTEN is set, an interrupt is generated if
— The software then reads the ACBST.XMIT bit to identi-
— ACBST.SDAST is set.
— ACBST.NMATCH, and ACBCTL1.NMINTE are set.
ACBST.SDAST is set to indicate that the buffer is emp-
ty.
both the INTEN and NMINTE bits in ACBCTL1 regis-
ters are set.
fy the direction requested by the master device. It
clears the ACBST.NMATCH bit so future byte transfers
are identified as data bytes.
SDA and SCL Pins Configuration
ACB Clock Frequency Configuration
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