CR16MCS9VJE8 National Semiconductor, CR16MCS9VJE8 Datasheet - Page 104

• Manufacturer Part Number: CR16MCS9VJE8
• Description: 16-Bit Microcontroller IC
• Manufacturer: National Semiconductor

Specifications of CR16MCS9VJE8

• Controller Family/series: CR16X
• Core Size: 16 Bit
• Program Memory Size: 64K X 8 Flash
• Digital Ic Case Style: PQFP
• No. Of Pins: 80
• Mounting Type: Surface Mount
• Clock Frequency: 25MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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20.7
CR16CAN has access to one interrupt vector in the CR16
CPU. The interrupt process can be initiated from the follow-
ing sources.
• CAN data transfer
• CAN error conditions is the detection of an CAN error.
The receive/transmit interrupt access to every message buff-
er can be individually enabled/disabled in the CIEN register.
The pending flags of the message buffer are located in the
CIPND register (read only) and can be cleared by resetting
the flags in the CICLR registers.
20.7.1
In order to reduce decoding time of the CIPND register, the
buffer interrupt request with the highest priority is placed as
interrupt status code into the IST[3:0] section of the CSTPND
register.
Each of the buffer interrupts as well as the error interrupt can
be individually enabled or disabled in the CAN Interrupt En-
able register (CIEN). As soon as an interrupt condition oc-
curs, every interrupt request is indicated by a flag in the CAN
Interrupt Pending register (CIPND). When the interrupt code
logic for the present highest priority interrupt request is en-
abled, this interrupt will be translated into the IST[3:0] bits of
the CAN Status Pending register (CSTPND). An interrupt re-
quest can be cleared by setting the corresponding bit in the
CAN Interrupt Clear register (CICLR) to ‘1’.
— Reception of a valid data frame in the buffer. (Buffer
— Successful transmission of a data frame. (Buffer state
— Successful response to a remote frame. (Buffer state
— Transmit scheduling. (Buffer state changes from
(The CEIPND bit in the CIPND register will be set as well
as the corresponding bits in the error diagnostic register
CEDIAG).
state changes from RX_READY to RX_FULL or
RX_OVERRUN).
changes from TX_ONCE to TX_NOT_ACTIVE or
RX_READY)
changes from TX_ONCE_RTR to TX_RTR).
TX_RTR to TX_ONCE_RTR).
Highest Priority Interrupt Code
INTERRUPTS
104
Figure67 illustrates the CR16CAN interrupt management.
The highest priority interrupt source is translated into the bits
IRQ and IST[3:0] as shown in Table24.
Table 24 Highest Priority Interrupt Code (ICEN=FFFF)
no request
Error interrupt
Buffer 0
Buffer 1
Buffer 2
Buffer 3
Buffer 4
Buffer 5
Buffer 6
Buffer 7
Buffer 8
Buffer 9
Buffer 10
Buffer 11
Buffer 12
Buffer 13
Buffer 14
CAN interrupt
request
Figure 67. CR16CAN Interrupt Management
CICEN
CICLR
CIPND
CIEN
IRQ
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IRQ
IST3
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
IST3
clear interrupt flags of every
message buffer individually
ICODE
IST2
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
IST2
IST1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
IST1
IST0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
IST0