IPSR-VIDEO Altera, IPSR-VIDEO Datasheet
IPSR-VIDEO
Specifications of IPSR-VIDEO
Related parts for IPSR-VIDEO
IPSR-VIDEO Summary of contents
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... Video and Image Processing Suite User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-VIPSUITE-10.1 Video and Image Processing Suite Document last updated for Altera Complete Design Suite version: Document publication date: User Guide 10.1 January 2011 Subscribe ...
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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...
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... Color Space Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–12 Control Synchronizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–12 Deinterlacer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–13 Frame Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–13 Frame Reader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–14 Gamma Corrector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–15 Interlacer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–15 Scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–16 Scaler 1–16 Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–17 Test Pattern Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–17 January 2011 Altera Corporation Contents Video and Image Processing Suite User Guide ...
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... Structure of Video Data Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7 Control Data Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7 Use of Control Data Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9 Structure of a Control Data Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9 Ancillary Data Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10 User-Defined and Altera-Reserved Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11 Packet Propagation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11 Video and Image Processing Suite User Guide Contents January 2011 Altera Corporation ...
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... Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–29 Active Format Description Inserter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–29 Color Plane Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–30 Rearranging Color Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–30 Combining Color Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–30 Splitting/Duplicating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–31 Subsampled Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–32 Avalon-ST Video Stream Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–32 January 2011 Altera Corporation v Video and Image Processing Suite User Guide ...
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... FIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–67 Error Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–67 2D Median Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–67 Error Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–67 Alpha Blending Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–67 Error Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–68 Chroma Resampler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–68 Error Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–69 Clipper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–69 Error Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–69 Video and Image Processing Suite User Guide Contents January 2011 Altera Corporation ...
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... Interlacer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–18 Scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–19 Scaler 6–20 Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–21 Test Pattern Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–23 Chapter 7. Control Register Maps 2D FIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1 Alpha Blending Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1 Clipper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–2 Clocked Video Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–3 January 2011 Altera Corporation vii Video and Image Processing Suite User Guide ...
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... Scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–13 Scaler 7–15 Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–16 Test Pattern Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–16 Additional Information Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2 Referenced Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–3 Video and Image Processing Suite User Guide Contents January 2011 Altera Corporation ...
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... This document describes the Altera IP cores that ease the development of video and image processing designs. You can use the following IP cores in a wide variety of image processing and display applications. The Video and Image Processing Suite contains the following MegaCore ■ “2D FIR Filter” ...
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... For more information about this release, refer to the and Errata. Device Family Support MegaCore functions can provide the types of support for target Altera device families described in Table 1–2. Altera IP Core Device Support Levels FPGA Device Families Preliminary—The core is verified with preliminary timing models for this device family ...
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... Avalon Memory-Mapped (Avalon-MM) interfaces for run-time control input and ■ connections to external memory blocks ■ Easy-to-use parameter editor for parameterization and hardware generation ■ IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators ■ Support for OpenCore Plus evaluation ■ SOPC Builder ready ...
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... Output at run time using an Avalon-MM slave interface. Color Plane Sequencer The Color Plane Sequencer MegaCore function changes how color plane samples are transmitted across the Avalon-ST interface. Video and Image Processing Suite User Guide Chapter 1: About This MegaCore Function Suite General Description January 2011 Altera Corporation ...
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... Gamma Corrector with a look-up table that models the nonlinear function to compensate for the non linearity. The look-up table can then transform the video data and give the best image on the display. January 2011 Altera Corporation 1–5 Video and Image Processing Suite User Guide ...
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... MegaCore function during the design cycle to validate a video system without the possible throughput issues associated with a real video input. Design Example A provided design example offers a starting point to quickly understand the Altera video design methodology, enabling you to build full video processing systems on an FPGA. ...
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... Stratix V (2) 1,011 Median filtering 64×64 pixel R’G’B frames using a 3×3 kernel of pixels. Cyclone IV GX (1) 1,529 January 2011 Altera Corporation ® II software targeting Cyclone IV GX and shows the performance figures for the 2D FIR Filter. Memory Logic Registers Bits ...
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... DSP Blocks f MAX (MHz) (9×9) (18×18) 4 — 200.72 — 2 324.36 — — 180.51 — — 294.2 — — 217.91 — — 309.98 6 — 219.88 — 6 317.86 January 2011 Altera Corporation ...
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... A 1080p60-compatible clipper with a runtime interface which uses offsets to set the clipping window. Cyclone IV GX (1) 661 Stratix V (2) 522 A 100×100 pixel clipper with a run-time interface which uses a rectangle to set the clipping window. January 2011 Altera Corporation Memory Logic Registers Bits M9K 2,353 16,384 — ...
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... Bits MLAB Bits 51,200 — 133.24 51,200 — 206.57 18,432 — 134.88 18,432 — 225.17 43,008 — 116.36 43,008 40 194.36 43,008 — 283.61 43,008 40 198.61 f MAX (MHz) Bits MLAB Bits 51,200 — 138.81 51,200 — 199.24 January 2011 Altera Corporation ...
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... Stratix V (2) 325 Rearranging 3 channels in sequence to 3 channels in parallel. 8 bit data. Cyclone IV GX (1) 231 Stratix V (2) 174 Notes to Table 1–11: (1) EP4CGX15BF14C6 devices. (2) 5SGXEA7H3F35C3 devices. January 2011 Altera Corporation Memory Logic Registers ALUTs M9K 307 — — 144 — — 325 — — ...
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... DSP Blocks f MAX (MHz) (9×9) (18×18) — — 209.69 — — 380.37 — — 212.27 — — 378.79 — — 211.77 — — 364.03 January 2011 Altera Corporation ...
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... Table 1–15. Frame Buffer Performance (Part Combinational Device Family LUTs/ALUTs Double-buffering XGA (1024×768) 8-bit RGB with a sequential data interface. Cyclone IV GX (1) 1,489 Stratix V (2) 1,100 January 2011 Altera Corporation Memory Logic Registers Bits M9K 750 — — 398 — — ...
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... DSP Blocks f MAX (MHz) (9×9) (18×18) — — 153.07 — — 287.85 — — 163.93 — — 295.77 — — 162.44 — — 289.10 — — 169.15 — — 310.85 January 2011 Altera Corporation ...
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... Interlacing 1080p 10-bit video, 2 channels over a parallel interface. Cyclone IV GX (1) 461 Stratix V (2) 302 Interlacing 1080p 10-bit video, 2 channels over a parallel interface, with runtime interlacing control. Cyclone IV GX (1) 528 January 2011 Altera Corporation Memory Logic Registers Bits M9K 271 10,260 3 153 10,260 ...
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... DSP Blocks f MAX (MHz) (9×9) (18×18) 4 — 203.67 — 4 336.47 — — 248.2 — — 354.99 19 — 182.95 — 19 227. 203.46 — 8 309.98 DSP Blocks f MAX (MHz) (9×9) (18×18) 4 — 181.52 — 5 279.96 January 2011 Altera Corporation ...
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... Producing a 400×x200, 8-bit 4:2:0 Y'Cb'Cr' stream with a parallel data interface. Cyclone IV GX (1) 159 Stratix V (2) 152 Producing a 640×480, 8-bit R'G'B' stream with a sequential data interface. Cyclone IV GX (1) 214 Stratix V (2) 161 January 2011 Altera Corporation Memory Logic Registers Bits M9K 4,016 417,936 — 3,101 417,936 — 1,909 70,512 — ...
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... Chapter 1: About This MegaCore Function Suite Performance and Resource Utilization DSP Blocks f MAX (MHz) (9×9) (18×18) — — 252.33 — — 482.39 — — 262.12 — — 374.25 January 2011 Altera Corporation ...
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... This chapter provides a general overview of the Altera IP core design flow to help you quickly get started with any Altera IP core. The Altera IP Library is installed as part of the Quartus II installation process. You can select and parameterize any Altera IP core from the library. Altera provides an integrated parameter editor that allows you to customize IP cores to support a wide variety of applications ...
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... Altera's Qsys system integration tool is now available as beta for evaluation in the Quartus II software subscription edition version 10.1. Altera does not recommend using the beta release of Qsys in the Quartus II software version 10.1 for designs that are close to completion and are meeting design requirements ...
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... Tools menu, and follow the prompts in the MegaWizard Plug-In Manager interface to create or edit a custom IP core variation select a specific Altera IP core, click the IP core in the Installed Plug-Ins list in the MegaWizard Plug-In Manager. 4. Specify the parameters on the Parameter Settings pages. For detailed explanations of these parameters, refer to the “ ...
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... For a complete list of models or libraries required to simulate your IP core, refer to the scripts provided with the testbench. For more information about simulating Altera IP cores, refer to Designs in volume 3 of the Quartus II Handbook. Video and Image Processing Suite User Guide ...
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... SOPC Builder defines default connections, which you can modify. The HDL files are ready to be compiled by the Quartus II software to produce output files for programming an Altera device. SOPC Builder generates a simulation testbench module for supported cores that includes basic transactions to validate the HDL files ...
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... In the Quartus II software, click Add/Remove Files in Project and add the .qip file to the project. 7. Compile your design in the Quartus II software. Video and Image Processing Suite User Guide Chapter 2: Getting Started with Altera IP Cores SOPC Builder Design Flow January 2011 Altera Corporation ...
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... During system generation, you can specify whether SOPC Builder generates a simulation model and testbench for the entire system, which you can use to easily simulate your system in any of Altera's supported simulation tools. SOPC Builder also generates a set of ModelSim the testbench and plain-text RTL design files that describe your system in the ModelSim simulation software ...
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... If your system is not part of a Quartus II project and you want to generate synthesis RTL files, turn on Create synthesis RTL files. Video and Image Processing Suite User Guide Chapter 2: Getting Started with Altera IP Cores Qsys System Integration Tool Design Flow section in volume 1 of the Quartus II Handbook and to Quartus ...
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... During system generation, Qsys generates a functional simulation model—or example design that includes a testbench—which you can use to simulate your system in any Altera-supported simulation tool. f For information about the latest Altera-supported simulation tools, refer to the Quartus II Software Release f For general information about simulating Altera IP cores, refer to Designs in volume 3 of the Quartus II Handbook ...
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... The <variation name> prefix is added automatically using the base output file name you specified in the parameter editor. Video and Image Processing Suite User Guide (Part Description TM Plug-In Manager flow, you are prompted to add the .qip file to the current Chapter 2: Getting Started with Altera IP Cores Generated Files January 2011 Altera Corporation ...
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... Settings tab. Figure 3–1. General Page of the Parameter Settings Tab of the 2D FIR Filter Parameter Editor The following sections describe the parameters for each MegaCore function. January 2011 Altera Corporation Cores. The parameter editor allows you to select only legal 3. Parameter Settings Chapter 2, Getting Started ...
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... This can be useful if you require a wider range output on an existing coefficient set. Choose the method for discarding fractional bits resulting from the FIR calculation. Choose the method for signed to unsigned conversion of the FIR results. Chapter 3: Parameter Settings 2D FIR Filter Description (1) (1) (2) (2) January 2011 Altera Corporation ...
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... Number of color 1–3 planes in sequence Filter size 3x3, 5x5 January 2011 Altera Corporation Description Choose the size in pixels of the convolution kernel used in the filtering. Turn on to enable run-time control of the coefficient values. You can choose a predefined set of simple smoothing or simple sharpening coefficients which are used for color model convolution at compile time ...
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... Choose the format/sampling rate format for the output frames. Note that the input and output formats must be different. Choose the algorithm to use in the horizontal direction when re-sampling data to or from 4:4:4. Chapter 3: Parameter Settings Alpha Blending Mixer January 2011 Altera Corporation ...
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... The left and right offset values must be less than or equal to the input image width. (2) The top and bottom offset values must be less than or equal to the input image height. January 2011 Altera Corporation Description Turn on to enable luma-adaptive mode. This mode looks at the luma channel during interpolation and uses this to detect edges ...
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... Choose the required FIFO depth in pixels (limited by the available on-chip memory). Turn on if you want to use the same signal for the input and output video image stream clocks. Turn on to use the optional stop/go control port. Chapter 3: Parameter Settings Clocked Video Input January 2011 Altera Corporation ...
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... Frame / Field 1: Vertical sync Default = 5 January 2011 Altera Corporation Description You can choose from a list of preset conversions or use the other fields in the dialog box to set up custom parameter values. If you click Load values into controls the dialog box is initialized with values for the selected preset conversion ...
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... Specifies whether the synchronization outputs are used Not used ■ Yes - Synchronization outputs, from the Clocked Video Input MegaCore ■ function, (sof, sof_locked) are used Specifies the width of the vid_std bus. Chapter 3: Parameter Settings Clocked Video Output January 2011 Altera Corporation ...
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... Turn on when stream contains two subsampled channels. For other MegaCore functions to be able to treat these channels as two fully sampled channels in sequence, the control packet width must be halved. January 2011 Altera Corporation Value Turn on to enable two pixels on each port. ...
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... Specify the output range minimum value. Specify the number of places to move the binary point. Choose the method of discarding fraction bits resulting from the calculation. Choose the method of signed to unsigned conversion for the results. Chapter 3: Parameter Settings Color Space Converter (CSC) Description January 2011 Altera Corporation ...
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... Editing these values change the actual coefficients and summands and the results values on the General page. Signed coefficients allow negative values; increasing the integer bits increases the magnitude range; and increasing the fraction bits increases the precision. January 2011 Altera Corporation Description Specifies a predefined set of coefficients and summands to use for color model conversion at compile time ...
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... Choose the number of color planes in parallel. Choose a default type for the initial field. The default value is not used if the first field is preceded by an Avalon-ST Control packet. Refer to “Deinterlacing Methods” on page Chapter 3: Parameter Settings Control Synchronizer Description Description 5–40. January 2011 Altera Corporation ...
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... Avalon-MM master ports 16, 32, 64,128, 256 width (3) January 2011 Altera Corporation Value Specifies whether external frame buffers are used buffering mode, data is piped directly from input to output without using external memory. This is possible only with the bob method. Double-buffering routes data via a pair of buffers in external memory ...
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... This MegaCore function does not support interlaced streams where fields are not of the same size (eg, for NTSC, F0 has 244 lines and F1 has 243 lines). Altera recommends that you use the clipper MegaCore function to crop the extra line in F0. (8) The weave and motion-adaptive algorithms stitch together F1 fields with the F0 fields that precede rather than follow them. ...
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... The Maximum packet length option is not available when the Number of packets buffered per frame is set to 0. (4) The number of frame buffers and the total memory required at the specified base address is displayed under the base address. January 2011 Altera Corporation Value Turn on to drop image data packets whose length is not ...
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... The number of color planes that are sent in sequence or parallel over one data connection. Specifies whether the specified number of color planes are transmitted in sequence or in parallel. For example, a value of 3 planes in sequence for R'G'B' R'G'B' R'G'B'. Chapter 3: Parameter Settings Frame Reader Description Description January 2011 Altera Corporation ...
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... Run-time control On or Off Control packets override On or Off field selection January 2011 Altera Corporation Value Specifies the maximum frame width in pixels. The maximum frame width is the default width at start up. Specifies the maximum progressive frame height in pixels. The maximum frame height is the default progressive height at start up ...
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... Specifies the number of bits to preserve between vertical and horizontal filtering. Turn on if you want the fixed-point type that stores the horizontal coefficients to have a sign bit. Chapter 3: Parameter Settings show the Scaler MegaCore Description Description January 2011 Altera Corporation Scaler ...
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... Coeff columns as a .csv file. Then in the parameter editor, select Custom from the Filter function list, click Browse, load the .csv file, and click Preview coefficients to verify the data. January 2011 Altera Corporation Specifies the number of integer bits for the fixed-point type used to store the horizontal coefficients. ...
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... Choose the number of vertical filter phases for the bicubic and polyphase algorithms. Choose the number of horizontal filter taps for the bicubic and polyphase algorithms. Choose the number of horizontal filter phases for the bicubic and polyphase algorithms. Chapter 3: Parameter Settings Scaler II 5–58. Description to 5–55. January 2011 Altera Corporation ...
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... Color planes are in parallel On or Off Number of input ports 1–12, Default = 2 Number of input ports (din and alpha_in). January 2011 Altera Corporation Value Turn on to force the algorithm to use signed vertical coefficient data. Choose the number of integer bits for each vertical coefficient. ...
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... Specifies whether to produce a progressive or an interlaced output stream. Choose the standard color bar or a uniform background. When pattern is uniform background, you can specify the individual R’G’B' or Y’ values depending on the currently selected color space. Chapter 3: Parameter Settings Test Pattern Generator January 2011 Altera Corporation ...
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... Figure 4–1 also have external interfaces that support clocked video standards. These MegaCore functions can connect between the function’s Avalon-ST interfaces and functions using clocked video standards such as BT.656. January 2011 Altera Corporation Avalon ST Connection DDR 2 Memory Function Avalon MM Master to Slave Connection ...
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... There are also seven packet types reserved for users, and seven packet types reserved for future definition by Altera. The packet type is defined by a 4-bit packet type identifier. This type identifier is the first value of any packet the symbol in the least significant bits of the interface. ...
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... January 2011 Altera Corporation Figure 4–2 on page 4–3 0 Video data packet User packet types Reserved for future Altera use 13 Ancillary data packet 14 Reserved for future Altera use 15 Control data packet Data of the packet (Split into symbols) X Start Packet type identifier X’s for unused symbols) “ ...
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... Y' CbCr (4:2:2) where Cb and Cr alternate between consecutive pixels. Figure 4–4. Horizontally Subsampled Y'CbCr Video and Image Processing Suite User Guide Symbol in most significant bits G R Symbol in least significant bits Chapter 4: Interfaces Avalon-ST Video Protocol January 2011 Altera Corporation ...
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... MegaCore functions of the Video and Image Processing Suite only process video data packets correctly if they use a certain set of color patterns. Chapter 5, Functional Descriptions MegaCore functions use. January 2011 Altera Corporation Plane for even rows Y Plane for odd rows Description Three color planes, B’ ...
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... Video and Image Processing Suite User Guide Recommended Color Patterns Parallel Sequence January 2011 Altera Corporation Chapter 4: Interfaces Avalon-ST Video Protocol ...
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... January 2011 Altera Corporation Bits per pixel Video Data, repeating a ...
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... The fields that follow are 1920 pixels wide and 540 pixels high. The next field is f1 (odd lines) and it is paired with the f0 field that precedes it. Chapter 4: Interfaces Avalon-ST Video Protocol Table 4–4 gives January 2011 Altera Corporation ...
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... This behavior may not be supported in future releases. Altera recommends for forward compatibility that functions implementing the protocol ensure there is a control data packet immediately preceding each video data packet. ...
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... X’s for unused symbols) Chapter 4: Interfaces Avalon-ST Video Protocol show examples of control data Symbols in most significant bits Symbols in middle significant bits Symbols in least significant bits End Symbols in most significant bits Symbols in least significant bits End January 2011 Altera Corporation ...
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... User-Defined and Altera-Reserved Packets The Avalon-ST Video protocol specifies that there are seven packet types reserved for use by users and seven packet types reserved for future use by Altera. The data content of all of these packets is undefined. However the structure must follow the rule that the packets are split into symbols as defined by the number color plane samples sent in one cycle of the color pattern ...
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... Width 1 1 bits_per_symbol × symbols_per_beat 1 1 Chapter 4: Interfaces Avalon-ST Video Protocol Avalon Table 4–7 does not show Direction Sink to Source Source to Sink Source to Sink Source to Sink Source to Sink January 2011 Altera Corporation ...
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... This example has one Avalon-ST port named din and one Avalon-ST port named dout. Data flows into the MegaCore function through din, is processed and flows out of the MegaCore function through dout. January 2011 Altera Corporation Parameter Color Pattern 3. 4. ...
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... Video and Image Processing Suite User Guide Figure 4–12 is: “Functional Descriptions” on page Specifications. All of the Avalon-ST interfaces that the Video and Chapter 4: Interfaces Avalon-ST Video Protocol 5–1. “Latency” on January 2011 Altera Corporation ...
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... Initially, din_ready is logic '1'. The source driving the input port sets din_valid to logic '1' and puts the blue color value B 2. The source holds din_valid at logic '1' and the green color value G 3. The corresponding red color value R January 2011 Altera Corporation Parameter Color Pattern 2. ...
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... Video and Image Processing Suite User Guide state that sinks may set ready to logic '0' at any time, for , which is legal because the ready latency of the interface means m+1,n Chapter 4: Interfaces Avalon-ST Video Protocol Avalon January 2011 Altera Corporation ...
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... If the Go bit is unset while data is being processed, then the MegaCore function stops processing data again at the beginning of the next image data packet and waits until the Go bit is set by external logic. January 2011 Altera Corporation 0x2 0x0 0x0 ...
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... MegaCore function has started processing the next frame (and therefore setting the Go bit to zero causes it to stop processing at the end of the next frame). Video and Image Processing Suite User Guide Chapter 4: Interfaces Avalon-MM Slave Interfaces ® II processor) to control the gamma corrector January 2011 Altera Corporation ...
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... Avalon-MM interfaces in multiple clock domains. Instead, the Avalon-MM slave interfaces must operate synchronously to the main clock and reset signals of the MegaCore function. The Avalon-MM slave interfaces must operate synchronously to this clock. January 2011 Altera Corporation until all frames are processed. ...
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... Input 1 Input 32 Output variable Output 1 Output 1 Output variable Output Table 4–11 are read-only and not required by a master interface Chapter 4: Interfaces Avalon-MM Master Interfaces Usage Read-Write (optional) Read-only Read-only Read-Write (optional) Read-write Read-write Read-write Read-only Write-only Write-only January 2011 Altera Corporation ...
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... Altera recommends that you keep the default values for Number of packets buffered per frame and Maximum packet length, unless you intend to extend the Avalon-ST Video protocol with custom packets. ...
Page 80
... Video and Image Processing Suite User Guide Chapter 4: Interfaces Buffering of Non-Image Data Packets in Memory January 2011 Altera Corporation ...
Page 81
... Result to Output Data Type Conversion After the calculation, the fixed point type of the results must be converted to the integer data type of the output. January 2011 Altera Corporation 5. Functional Descriptions Video and Image Processing Suite User Guide ...
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... Where this kernel runs over the edge of the input image, zeros are filled in. Video and Image Processing Suite User Guide 5–1. Value and can be any color plane: , Chapter 5: Functional Descriptions 2D Median Filter α β γ January 2011 Altera Corporation ...
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... At this stage, the on/off status of each layer is read. A layer can be disabled (0), active and displayed (1) or consumed but not displayed (2). The maximum number of image layers mixed cannot be changed dynamically and must be set in the parameter editor for the Alpha Blending Mixer. January 2011 Altera Corporation Table 5–2. Value ...
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... Video and Image Processing Suite User Guide (disable/displayed/consumed) 4–17. For details of the control register maps, 7–2. For information about the Avalon-MM interface Table 6–3 on page 6–2. Chapter 5: Functional Descriptions Alpha Blending Mixer layers internal registers January 2011 Altera Corporation ...
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... One, two or three channels in sequence or in parallel as selected in the Color Pattern (din and parameter editor. For example, if three channels in sequence is selected where dout) , and , Color Pattern (alpha_in) A single color plane representing the alpha value for each pixel: January 2011 Altera Corporation , where N is the maximum number of layers – ...
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... It works by simply discarding the Cb and Cr samples that occur on even columns (assuming the first column is numbered 1). This algorithm is very fast and cheap but, due to aliasing effects, it does not produce the best image quality. Video and Image Processing Suite User Guide Sample Chapter 5: Functional Descriptions Chroma Resampler January 2011 Altera Corporation ...
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... This makes the interpolated chroma samples line up better with edges in the luma channel and is particularly noticeable for bold synthetic edges such as text. January 2011 Altera Corporation (“Choosing and Loading 5–58) that the Scaler MegaCore function uses. Their quantized shows 4:2:2 data at an edge transition ...
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... For more information about how non-video packets are transferred, refer to Propagation” on page Video and Image Processing Suite User Guide CbCr Color + + Value Y’ Intensity 5–3. Sample 4–11. Chapter 5: Functional Descriptions Chroma Resampler + + Sample – 1]. All output data “Packet January 2011 Altera Corporation ...
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... Number of bits per color sample selected in the parameter editor. Any combination of one, two, three, or four channels in each of sequence or Color Pattern parallel. For example, if three channels in sequence is selected where , , and can be any color plane: January 2011 Altera Corporation Table 5–4. Value For 4:2:2 sequential data: ...
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... When in 10-bit mode the bottom 2 bits of the TRS and XYZ words are ignored to allow easy transition from an 8-bit system. Video and Image Processing Suite User Guide Chapter 5: Functional Descriptions Figure 5–4. 3FF 0 0 XYZ TRS (10bit) January 2011 Altera Corporation Clocked Video Input ...
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... The Clocked Video Input MegaCore function only reads vid_data when vid_datavalid is high (as in the embedded synchronization format) but it treats each read sample as active picture data. January 2011 Altera Corporation Table 5–6. 8-bit These bits are not inspected by the Clocked Video Input MegaCore [3:0] function ...
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... When asserted the video active picture period (not horizontal or vertical blanking). When 1, the video horizontal synchronization period. When 1, the video vertical synchronization period. When 1, the video is interlaced and in field 1. When 0, the video is either progressive or interlaced and in field Chapter 5: Functional Descriptions Clocked Video Input Dn+1 Dn+2 January 2011 Altera Corporation ...
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... Standard—The MegaCore function provides the contents of the vid_std bus via the Standard register. When connected to the rx_std signal of a SDI MegaCore function, for example, these values can be used to report the standard (SD, HD, or 3G) of the incoming video. January 2011 Altera Corporation Field Order F1 first Start, F1, F0, ..., F1, F0, Stop F0 first Start, F0, F1, ...
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... Stable bit set and interrupt fired 0 —Two of last three lines had the same sample count. 0 End of first field of video. Interlaced bit set—Start of 0 second field of video. 562 End of second field of video. Resolution valid bit set and 562 interrupt fired. January 2011 Altera Corporation ...
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... An example of how to set up the Clocked Video Input to output an SOF signal aligned to the incoming video synchronization (in embedded synchronization mode) is included in Table Table 5–10. Example of Clocked Video Input To Output an SOF Signal Format SOF Sample Register 720p60 1080i60 NTSC January 2011 Altera Corporation shows an example configuration ...
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... If the packet is an AFD packet (DID = 0x41, SDID = 0x5), the extractor places the contents of the ancillary packet into the AFD Extractor register map. Video and Image Processing Suite User Guide Chapter 5: Functional Descriptions Clocked Video Input January 2011 Altera Corporation ...
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... January 2011 Altera Corporation Register When bit the core discards all packets. Control When bit the core passes through all non- ancillary packets ...
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... The Clocked Video Output MegaCore function creates a video frame consisting of horizontal and vertical blanking (containing syncs) and areas of active picture (taken from the Avalon-ST Video input). Video and Image Processing Suite User Guide Chapter 5: Functional Descriptions Clocked Video Output January 2011 Altera Corporation ...
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... Chapter 5: Functional Descriptions Clocked Video Output The format of the video frame is shown in on page 5–20 Figure 5–8. Progressive Frame Format January 2011 Altera Corporation Figure 5–8 for interlaced. Horizontal Sync F0 Active Picture Width Vertical Blanking 5–19 for progressive and Figure 5–9 ...
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... Video and Image Processing Suite User Guide Horizontal Sync F0 Active Picture Width F0 Vertical Blanking F1 Active Picture Width Vertical Blanking (Table 5–6 on page 5–11). Chapter 5: Functional Descriptions Clocked Video Output “Ancillary Data Packets” on January 2011 Altera Corporation ...
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... Avalon-MM control port. If you turn off Use control port in the parameter editor for the Clocked Video Output, then the output video format always has the format specified in the parameter editor. January 2011 Altera Corporation Description 1 during the horizontal synchronization period. 1 during the vertical synchronization period. ...
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... Ancillary line H front porch H blanking Video and Image Processing Suite User Guide “Video Formats” on page 5–18. F0 active picture H H back sync Active samples porch Chapter 5: Functional Descriptions Clocked Video Output V front porch V sync V back porch January 2011 Altera Corporation ...
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... Line line ModeN Valid N/A ModeN Ancillary Line Ancillary line January 2011 Altera Corporation Figure 5–10 relates to the register map. Description The zeroth bit of this register is the Interlaced bit: Set to 0 for progressive. Bit 1 of this register is the sequential output ■ ...
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... Video and Image Processing Suite User Guide “Video Formats” on page 5–18. F0 active picture F1 active picture H back Active samples porch Chapter 5: Functional Descriptions Clocked Video Output F0 V front porch F0 V sync F0 V back porch V front porch V sync V back porch January 2011 Altera Corporation ...
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... F falling edge line ModeN Valid N/A ModeN Ancillary Line Ancillary line ModeN F0 Ancillary Line F0 ancillary line January 2011 Altera Corporation Figure 5–11 relates to the register map. Description The zeroth bit of this register is the Interlaced bit: Set to 0 for interlaced. ■ Bit 1 of this register is the sequential output control bit (only if the Allow ■ ...
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... Control register. When Genlock functionality is enabled the Clocked Video Output MegaCore does not synchronize itself to the incoming Avalon-ST Video. Altera recommends that you disable Genlock functionality before changing output mode and then only enable it again when the status update interrupt has fired, indicating that the mode change has occurred ...
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... Vcoclk Divider register), the Clocked Video Output does not alter the output video. If your PFD clock tracking has a delay associated with it, Altera recommends that even if the vcoclk_div signal is not being used, the Vcoclk Divider register should be set to a threshold value e ...
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... In addition to the underflow bit, the current level of the FIFO can be read from the Used Words register. Video and Image Processing Suite User Guide Phase Detector Charge Divider + Pump - Feedback Divider sof sof_locked Chapter 5: Functional Descriptions Clocked Video Output 27 MHz VCXO vid_clk Clocked SDI Video TX Output January 2011 Altera Corporation ...
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... Table 5–15. AFD Inserter Register Map Address January 2011 Altera Corporation Register When bit the core discards all packets. Control When bit the core passes through all non- ancillary packets. Reserved. Reserved. AFD Bits 0-3 contain the active format description code. AR Bit 0 contains the aspect ratio code ...
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... Video and Image Processing Suite User Guide shows an example that rearranges the color pattern Chapter 5: Functional Descriptions Color Plane Sequencer “Avalon-ST Video Protocol” Color pattern of a video data packet on the output stream 3 color plane samples in parallel January 2011 Altera Corporation ...
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... This allows for splitting of video data packets, duplication of video data packets mix of splitting and duplication. The output color patterns are independent of each other, so the arrangement of one output stream's color pattern places no limitation on the arrangement of the other output stream's color pattern. January 2011 Altera Corporation ...
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... Chapter 5: Functional Descriptions Color Plane Sequencer R G Color pattern of a video data packet on output stream 0 2 color plane samples in parallel G B Color pattern of a video data packet on output stream 1 2 color plane samples in sequence Table 5–16. Value January 2011 Altera Corporation ...
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... Computer B’G’R’ to CbCrY’: SDTV ■ CbCrY’: SDTV to Computer B’G’R’ ■ Computer B’G’R’ to CbCrY’: HDTV ■ CbCrY’: HDTV to Computer B’G’R’ January 2011 Altera Corporation 5–33 Video and Image Processing Suite User Guide ...
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... After the calculation, the fixed point type of the results must be converted to the integer data type of the output. This conversion is performed in four stages, in the following order: Video and Image Processing Suite User Guide Chapter 5: Functional Descriptions Color Space Converter January 2011 Altera Corporation ...
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... Notes to Table (1) For channels in parallel, the top of the color pattern matrix represents the MSB of data and the bottom represents the LSB. For details, refer to January 2011 Altera Corporation inTable 5–17. Read from control packets at run time. Read from control packets at run time. ...
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... Scaler, which means that the Scaler cannot be configured in advance of a certain video data packet. The Control Synchronizer solves this problem, as described in the following scenario. Video and Image Processing Suite User Guide Chapter 5: Functional Descriptions Control Synchronizer January 2011 Altera Corporation ...
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... Red Line Indicates Control Data Packet and Video Data Packet Pair Number 5 (Width 320) Blue Line Indicates Control Data Packet and Video Data Packet Pair Number 1 (Width 640) Control Data Packet and Video Data Packet Pair Numbers 2, 3, and 4 are Stored in the Frame Buffer January 2011 Altera Corporation Avalon MM Frame ...
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... Chapter 5: Functional Descriptions Control Synchronizer Control Synchronizer Writes the Data to the Specified Addresses. This Configures the Scaler to an Output Width of 320 Avalon MM Avalon MM Master Control Scaler Synchronizer Avalon MM Figure 5–20. Avalon MM Avalon MM Master Control Scaler Synchronizer Avalon MM Value January 2011 Altera Corporation ...
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... the current field has to be made at compile time. The deinterlacing algorithm does not adapt itself to handle PsF content. January 2011 Altera Corporation Value Number of bits per color sample selected in the parameter editor four color planes in parallel, with any number of color planes in sequence. “ ...
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... The Deinterlacer does not support interlaced streams where F0 fields are one line higher than F1 fields in most of its parameterizations. (Bob with one output frame for each input frame is the only exception.) Altera recommends using the Clipper MegaCore function to feed the Deinterlacer with an interlaced video stream that it can support ...
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... The next stored motion value is an average of the computed motion and of the ■ stored motion This computed motion means that the motion that the blending algorithm uses climbs up immediately, but takes about four or five frames to stabilize. January 2011 Altera Corporation 5–41 Video and Image Processing Suite User Guide ...
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... Video and Image Processing Suite User Guide (Figure Previous Frame Upper Pixel + Lower Pixel Output Pixel = Chapter 5: Functional Descriptions Deinterlacer 5–22 Current Field (C) X Figure 5–23shows the Current Frame , + ( Still Pixel January 2011 Altera Corporation ...
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... The last frame buffer is spare. January 2011 Altera Corporation 5–43 Video and Image Processing Suite User Guide ...
Page 124
... Video and Image Processing Suite User Guide Chapter 5: Functional Descriptions Deinterlacer January 2011 Altera Corporation ...
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... Handling of Avalon-ST Video Control Packets When buffering is used, the Deinterlacer MegaCore function stores non-image data packets in memory as described in Memory” on page January 2011 Altera Corporation “Buffering of Non-Image Data Packets in 4–21. 5–45 Table 7–8 on ...
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... The Frame Buffer is built with two basic blocks: a writer which stores input pixels in memory and a reader which retrieves video frames from the memory and outputs them. Video and Image Processing Suite User Guide 5–19. Value Chapter 5: Functional Descriptions Frame Buffer Table 4–4 on page 4–8.) α β γ and , January 2011 Altera Corporation ...
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... If dropping frames is not allowed, the writer component stalls until the reader component has finished its frame and replaced the spare buffer with a dirty buffer. January 2011 Altera Corporation Memory Writer ...
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... For more information, refer to Video and Image Processing Suite User Guide describes the control register maps for the Frame Buffer “Control Data Packets” on page Chapter 5: Functional Descriptions Frame Buffer 4–7. January 2011 Altera Corporation ...
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... The Frame Reader has an Avalon-ST source on which it streams video data using the Avalon-ST Video protocol. The Frame Reader also has an Avalon slave port, which provides the MegaCore function with configuration data. January 2011 Altera Corporation “Buffering of Non-Image Data Packets in Memory” on page 5–49. ...
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... Frame Reader MegaCore, which is configured for: ■ 8 bits per pixel per color plane ■ 3 color planes in parallel ■ Master port width 64 Video and Image Processing Suite User Guide Chapter 5: Functional Descriptions Frame Reader January 2011 Altera Corporation ...
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... The Avalon-ST Video parameters for the Frame Reader MegaCore function are shown in Table 5–21. Table 5–21. Avalon-ST Video Parameters (Part Parameter Frame Width Frame Height Interlaced / Progressive January 2011 Altera Corporation Table 5–21 ...
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... Image Table 5–22. Value and can be any color plane: Chapter 5: Functional Descriptions Gamma Corrector Value Table 7–13 on page 7–12, 7–12. For information about the 6–17. α β January 2011 Altera Corporation γ ...
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... Video and Image Processing Suite, refer to page 4–17. For details of the register map for the Scaler MegaCore function, refer to Table 7–17 on page January 2011 Altera Corporation Table 7–16 on page 7–13 5–23. The Interlacer does not support vertically subsampled video Value “Avalon-MM Slave Interfaces” on 7– ...
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... Video and Image Processing Suite User Guide and h respectively. The width and height of the output image in in and the function that returns an intensity value for a given out out /w , (j+0. out in out × )/(2 × × out Chapter 5: Functional Descriptions × )/(2 × out January 2011 Altera Corporation Scaler ...
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... In the following discussion, all comments relating to the polyphase algorithm are applicable to the bicubic algorithm assuming 4×4 taps. January 2011 Altera Corporation )/w in out ...
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... Line Buffer Delay Cv 1 Bit Narrowing Register Delay Ch 1 Bit Narrowing “Algorithmic Description” on page Chapter 5: Functional Descriptions Scaler Line Buffer Delay Cv Nv Register Delay Ch Nh 5–58. vertical taps and N horizontal v h January 2011 Altera Corporation ...
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... Choosing to have more memory banks allows for each bank to contain coefficients for a specific scaling ratio and for coefficient changes to be accomplished very quickly by changing the read bank. Alternatively, for memory-sensitive applications, use a single bank and coefficient writes have an immediate effect on data processing. January 2011 Altera Corporation + N per channel in parallel. The width of each v ...
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... As in the bilinear case, to produce out phase = --------------------------------------------------------- - i max out out phase = ------------------------------------------------------ - j max out 7–13). shows how a 2-lobe Lanczos-windowed sinc function Chapter 5: Functional Descriptions Scaler × û, in û) where in and page 5–55. The results produce a single value. i January 2011 Altera Corporation ...
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... The sum of any two coefficients in the same phase must also be in the declared range. For example, if there is 1 integer bit, 7 fraction bits, and a sign bit, each value and the sum of any two values should be in the range [–256, 255] representing the range [-2, 1.9921875]. January 2011 Altera Corporation 1 sin x ...
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... The parameters which have the largest effect are the number of taps and the filter function chosen to provide the coefficients. The number of phases and number of bits of precision are less important to the image quality. Video and Image Processing Suite User Guide Chapter 5: Functional Descriptions Scaler {0, 1/ – 1/P)}, January 2011 Altera Corporation ...
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... Each output from the Switch can be driven by only one input and each input to the Switch can drive only one output. Any input can be disabled that is not routed to an output, which stalls the input by pulling it's ready signal low. January 2011 Altera Corporation Taps Phases ...
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... Switch and Alpha Blending Mixer. The following sequence shows an example for layer switching: Video and Image Processing Suite User Guide Background Layer Alpha Blending Layer 1 Mixer MegaCore Function Layer 2 Chapter 5: Functional Descriptions Switch Control Synchronizer MegaCore Function Avalon-MM Master January 2011 Altera Corporation ...
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... Figure 5–29. Color Bar Pattern January 2011 Altera Corporation Table 3–22 on page 3–21. For information about the run-time control Table 7–20 on page 7– ...
Page 144
... Chapter 5: Functional Descriptions Table 5–26 (assuming 8 bits per color R’G’B’ (180,180,180) (180,128,128) (180,180,16) (162,44,142) (16,180,180) (131,156,44) (16,180,16) (112,72,58) (180,16,180) (84,184,198) (180,16,16) (65,100,212) (16,16,180) (35,212,114) (16,16,16) (16,128,128) Table 7–21 on page 7–17. is slightly modified: Test Pattern Generator Y’CbCr January 2011 Altera Corporation ...
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... The Test Pattern Generator cannot produce interlaced streams of pixel data with an odd frame height. To create interlaced video streams where F0 fields are one line higher than F1 fields, Altera recommends feeding Test Pattern Generator progressive video output into the Interlacer MegaCore function. Table 5–27. Test Pattern Generator Avalon-ST Video Protocol Parameters (Part Parameter Width selected in the parameter editor ...
Page 146
... Video and Image Processing Suite User Guide Chapter 5: Functional Descriptions Stall Behavior and Error Recovery Value For RGB parallel data: For 4:2:2 sequential data For 4:2:2 parallel data: Y For 4:2:0 parallel data January 2011 Altera Corporation ...
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... Between frames, the Alpha Blending Mixer is processing non-image data packets from its input layers in sequential order and may exert backpressure during the process until the image data header has been received for all its input. January 2011 Altera Corporation 5–67 Video and Image Processing Suite User Guide ...
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... For example, the subsampled side pauses for one third of the clock cycles in the 4:2:2 case or half of the clock cycles in the 4:2:0 case. Video and Image Processing Suite User Guide Chapter 5: Functional Descriptions Stall Behavior and Error Recovery January 2011 Altera Corporation ...
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... Color Plane Sequencer The Color Plane Sequencer MegaCore function stalls for approximately 10 cycles after processing each line of a video frame. Between frames the MegaCore function stalls for approximately 30 cycles. January 2011 Altera Corporation 5–69 Video and Image Processing Suite User Guide ...
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... The delay from input to output is just a few clock cycles. While a field is being discarded, input is read at the maximum rate and no output is generated. Video and Image Processing Suite User Guide Chapter 5: Functional Descriptions Stall Behavior and Error Recovery January 2011 Altera Corporation ...
Page 151
... The Frame Buffer MegaCore function may stall frequently and read or write less than once per clock cycle during control packet processing. During data processing at the input or at the output, the stall behavior of the Frame Buffer is largely decided by contention on the memory bus. January 2011 Altera Corporation 5–71 Video and Image Processing Suite User Guide ...
Page 152
... When an early endofpacket signal is received, the current output field is interrupted as soon as possible and may be padded with a single undefined pixel. Video and Image Processing Suite User Guide Chapter 5: Functional Descriptions Stall Behavior and Error Recovery January 2011 Altera Corporation ...
Page 153
... On receiving an early endofpacket signal, the Scaler stalls its input but continues writing data until it has sent an entire frame does not receive an endofpacket signal at the end of a frame, the Scaler discards data until the end-of-packet is found. January 2011 Altera Corporation vertical taps, N – 1 lines of input are read into line ...
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... Before switching its outputs it synchronize all its inputs and during this synchronization the inputs may be stalled. Video and Image Processing Suite User Guide Chapter 5: Functional Descriptions Stall Behavior and Error Recovery vertical taps, N – 1 lines of input are read into line v v January 2011 Altera Corporation ...
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... All modes with Video in and out use the same clock: On (2) Color Plane Sequencer All modes Color Space Converter All modes Control Synchronizer All modes January 2011 Altera Corporation 5–75 Latency (Note 1) (N–1) lines +O (cycles) (N–1) lines +O (cycles) O (cycles) O (cycles) ...
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... O (lines). Video and Image Processing Suite User Guide Chapter 5: Functional Descriptions Latency Latency (Note 1) O (cycles) 1 frame +O (lines) 1 field +O (lines) 1 frame +O (lines) 1 frame +O lines N/A O (cycles) O (cycles) (N–1) lines +O (cycles) (N–1) lines +O (cycles) 2 cycles N/A January 2011 Altera Corporation ...
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... Out dout_startofpacket Out dout_valid January 2011 Altera Corporation Table 6–19 list the input and output signals for the Video and Image The main system clock. The MegaCore function operates on the rising edge of the clock signal. The MegaCore function is asynchronously reset when reset is asserted high. ...
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... The reset must be de-asserted synchronously with respect to the rising edge of the clock signal. alpha_in_N port Avalon-ST data bus for layer N. Pixel data is In transferred into the MegaCore function over this bus. Chapter 6: Signals 2D Median Filter Description (1) January 2011 Altera Corporation ...
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... These ports are present only if Alpha blending the parameter editor. Note that alpha channel ports are created for layer zero even though no alpha mixing is possible for layer zero (the background layer). These ports are ignored and can safely be left unconnected or tied to 0. January 2011 Altera Corporation Direction alpha_in_N port Avalon-ST endofpacket signal ...
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... Avalon-MM address bus. Specifies a word offset into the slave address space. (1) control slave port Avalon-MM chipselect signal. The control port ignores all other signals unless this signal is asserted. Chapter 6: Signals Chroma Resampler (1) January 2011 Altera Corporation ...
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... In vid_clk In av_address In av_read January 2011 Altera Corporation control slave port Avalon-MM readdata bus. These output lines are used for read transfers. (1) control slave port Avalon-MM waitrequest signal. control slave port Avalon-MM write signal. When this signal is asserted, the control port accepts new data from the writedata bus. ...
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... Clocked video color plane format selection signal (in run-time switching of color plane transmission formats mode only). This signal distinguishes between sequential (when low) and parallel (when high) color plane formats. Chapter 6: Signals Clocked Video Input (1) (1) January 2011 Altera Corporation ...
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... In is_sop In is_valid January 2011 Altera Corporation Description Clocked video locked signal. This signal is asserted when a stable video stream is present on the input. This signal is de-asserted when the video stream is removed. Video Standard bus. Can be connected to the rx_std signal of the SDI MegaCore function (or any other interface) to read from the Standard register ...
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... Synchronization Mode Only.) Clocked video vertical blanking signal. This signal is asserted during the vertical blanking period of the video stream. (Separate Synchronization Mode Only.) Clocked video vertical synchronization signal. This signal is asserted during the vertical synchronization period of the video stream. Chapter 6: Signals Clocked Video Output (1) January 2011 Altera Corporation ...
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... In reset In din_data January 2011 Altera Corporation Description The main system clock. The MegaCore function operates on the rising edge of the clock signal. The MegaCore function is asynchronously reset when reset is asserted high. The reset must be de-asserted synchronously with respect to the rising edge of the clock signal ...
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... Avalon-ST data bus. Pixel data is transferred out of the MegaCore function over this bus. dout port Avalon-ST endofpacket signal. This signal marks the end of an Avalon-ST packet. Chapter 6: Signals Control Synchronizer January 2011 Altera Corporation ...
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... Table 6–11. Deinterlacer Signals (Part Signal clock reset din_data din_endofpacket January 2011 Altera Corporation Description dout port Avalon-ST ready signal. This signal is asserted by the downstream device when it is able to receive data. dout port Avalon-ST startofpacket signal. This signal marks the start of an Avalon-ST packet. ...
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... Avalon-MM write signal. When In asserted, the ma_control port accepts new data from the writedata bus. (5) ma_control slave port Avalon-MM writedata bus. These In input lines are used for write transfers. Chapter 6: Signals Deinterlacer (6) (6) (6) (6) (5) (5) (5) January 2011 Altera Corporation ...
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... January 2011 Altera Corporation Direction Description read_master_N port Avalon-MM address bus. Specifies Out a byte address in the Avalon-MM address space. (1), (2), (3) read_master_N port Avalon-MM burstcount signal. Out Specifies the number of transfers in each burst. (1), (2), (3) read_master_N port clock signal ...
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... Avalon-ST packet. dout port Avalon-ST valid signal. This signal is asserted when Out the MegaCore function is outputs data. read_master port Avalon-MM address bus. Specifies a byte Out address in the Avalon-MM address space. Chapter 6: Signals Frame Buffer Description (3) Description January 2011 Altera Corporation ...
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... January 2011 Altera Corporation Direction read_master port Avalon-MM burstcount signal. Specifies the Out number of transfers in each burst. read_master port The clock signal. The interface operates on the In rising edge of the clock signal. read_master port Avalon-MM read signal. Asserted to indicate Out read requests from the master to the system interconnect fabric ...
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... Avalon-MM readdata bus. These output Out lines are used for read transfers. slave port Avalon-MM write signal. When this signal is In asserted, the gamma_lut port accepts new data from the writedata bus. Chapter 6: Signals Frame Reader Description (3) (3) (3) Description January 2011 Altera Corporation ...
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... In reset In din_data In din_endofpacket Out din_ready January 2011 Altera Corporation Direction slave port Avalon-MM writedata bus. These input In lines are used for write transfers. slave port Avalon-MM interrupt signal. When asserted the interrupt registers of the MegaCore function have Out been updated and the master should read them to determine what has occurred ...
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... Avalon-MM readdata bus. These output lines are used for read transfers. (1) control slave port Avalon-MM waitrequest signal. control slave port Avalon-MM write signal. When this signal is asserted, the control port accepts new data from the writedata bus. Chapter 6: Signals Interlacer (1) (1) (1) January 2011 Altera Corporation ...
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... Out control_av_readdata Out control_av_waitrequest In control_av_write January 2011 Altera Corporation Description control slave port Avalon-MM writedata bus. These input lines are used for write transfers. (1) din port Avalon-ST data bus. Pixel data is transferred into the MegaCore function over this bus. din port Avalon-ST endofpacket signal. This signal marks the end of an Avalon-ST packet ...
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... During reads, byteenable indicates which bytes the master is reading. Slaves that simply return readdata with no side effects are free to ignore byteenable during reads. (1) Chapter 6: Signals Scaler II January 2011 Altera Corporation ...
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... Table 6–18. Switch Signals (Part Signal clock reset January 2011 Altera Corporation control slave port Avalon-MM read signal. When you assert this signal, the control port outputs new data at readdata. control slave port Avalon-MM readdata bus. Output lines for read transfers. ...
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... Avalon-ST startofpacket signal. This signal marks the Out start of an Avalon-ST packet. dout_N port Avalon-ST valid signal. This signal is asserted when the Out MegaCore function outputs data. Chapter 6: Signals Switch Description (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) January 2011 Altera Corporation ...
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... Note to Table 6–19 (1) These ports are present only if Runtime control of image size the parameter editor. January 2011 Altera Corporation Description The main system clock. The MegaCore function operates on the rising edge of the clock signal. The MegaCore function is asynchronously reset when reset is asserted high ...
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... Video and Image Processing Suite User Guide Chapter 6: Signals Test Pattern Generator January 2011 Altera Corporation ...
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... Coefficient n ■ Alpha Blending Mixer Table 7–2 describes the Alpha Blending Mixer MegaCore function control register map. January 2011 Altera Corporation 7. Control Register Maps “Avalon-MM Slave Interfaces” on page Description “Avalon-MM Slave Interfaces” on page 4–17 for full details. Row (where 0 is the top row of the kernel) is the integer value via the truncation of (n– ...
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... Video and Image Processing Suite User Guide Description for full details. for full details. describes the Clipper MegaCore function control register map. Description for full details. for full details. (1) Chapter 7: Control Register Maps Clipper “Avalon-MM Slave (1) (1) “Avalon-MM Slave Interfaces” on (1) (2) January 2011 Altera Corporation ...
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... Table 7–4. Clocked Video Input Control Register Map (Part Address Register 0 Control 1 Status January 2011 Altera Corporation Description (2) Description Bit 0 of this register is the Go bit: Setting this bit to 1 causes the Clocked Video Input MegaCore function to ■ start data output on the next video frame boundary. Refer to on page 5– ...
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... Bits 2–15 are the sample value. ■ Start of frame line register. The line upon which the SOF occurs measured from the rising edge of the F0 vertical sync. Number of cycles of vid_clk (refclk) before refclk_div signal triggers. Chapter 7: Control Register Maps Clocked Video Input January 2011 Altera Corporation ...
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... Mode1 Sample Count 7 Mode1 F0 Line Count 8 Mode1 F1 Line Count January 2011 Altera Corporation Description Bit 0 of this register is the Go bit: Setting this bit to 1 causes the Clocked Video Output MegaCore function to ■ start video data output. Refer to “Control Port” on page 5–21 Bits 3, 2, and 1 of the Control register are the interrupt enables: Setting bit enables the status update interrupt ...
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... The line to start inserting ancillary data packets. The line in field F0 to start inserting ancillary data packets. Video mode 1 valid. Set to indicate that this mode is valid and can be used for video output. ... ... Chapter 7: Control Register Maps Clocked Video Output January 2011 Altera Corporation ...
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... Setting bit enables the completion of writes interrupt. Bit 0 of this register is the Status bit. All other bits are unused. Refer to 1 Status Slave Interfaces” on page 4–17 January 2011 Altera Corporation Description “Avalon-MM Slave Interfaces” on page 4–17 for full details. “Color Space Conversion” on page ...
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... An run-time control interface can be attached to the Deinterlacer that you can use to override the default behavior of the motion-adaptive algorithm or to synchronize the input and output frame rates. However not possible to enable both interfaces simultaneously. Video and Image Processing Suite User Guide Chapter 7: Control Register Maps Description January 2011 Altera Corporation Deinterlacer ...
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... Frame Buffer A run-time control can be attached either to the writer component or to the reader component of the Frame Buffer MegaCore function but not to both. The width of each register is 16 bits. January 2011 Altera Corporation Description for full details. for full details. Description for full details ...
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... Video and Image Processing Suite User Guide Description “Avalon-MM Slave Interfaces” on page 4–17 for full details. Description “Avalon-MM Slave Interfaces” on page 4–17 for full details. Chapter 7: Control Register Maps Frame Buffer for full details. “Avalon-MM for full details. “Avalon-MM January 2011 Altera Corporation ...
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... Gamma Corrector The Gamma Corrector can have up to three Avalon-MM slave interfaces. There is a separate slave interface for each channel in parallel. Table 7–15 on page 7–12 January 2011 Altera Corporation describes the Frame Reader runtime control registers. Description for full details. Table describe the control register maps for these interfaces ...
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... MegaCore function. To ensure that gamma look-up values do not change during processing of a video frame, use the Go bit in Interface 0 to stop the MegaCore function while the table is changed. Chapter 7: Control Register Maps Gamma Corrector “Avalon-MM Slave for full “Avalon- January 2011 Altera Corporation ...
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... Status 2 Output Width 3 Output Height January 2011 Altera Corporation Description for full details. Description Bit 0 of this register is the Go bit, all other bits are unused. Setting this bit to 0, causes the Scaler to stop the next time that control information is read. Refer to “ ...
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... Setting up Tap 2 for Phase 1. –1 Setting up Tap 3 for Phase 1. 1 Commit the writes to Phase 1. ... ... –1 Setting up Tap 0 for Phase 7. 13 Setting up Tap 1 for Phase 7. 124 Setting up Tap 2 for Phase 7. Chapter 7: Control Register Maps Description (2) (2) Purpose January 2011 Altera Corporation Scaler ...
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... Bank Vertical Coefficient Read 8 Bank 9 Horizontal Phase January 2011 Altera Corporation Value –8 Setting up Tap 3 for Phase 7. 7 Commit the writes to Phase 7. Bit 0 of this register is the Go bit, all other bits are unused. Setting this bit to 0, causes the Scaler II to stop the next time that control information is read ...
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... For example, for a 3 input switch: 3'b000 = no output ■ 3'b001 = din_0 ■ 3'b010 = din_1 ■ 3'b100 = din_2 ■ As Dout0 Output Control but for output dout1. ... As Dout0 Output Control but for output dout12. Chapter 7: Control Register Maps Switch January 2011 Altera Corporation ...
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... These control registers are only available when the test pattern generator MegaCore function is configured to output a uniform color background and when the run-time control interface has been enabled. January 2011 Altera Corporation Description “Generation of Avalon-ST Video Control Packets and Run-Time Control” on for full details. “ ...
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... Video and Image Processing Suite User Guide Chapter 7: Control Register Maps Test Pattern Generator January 2011 Altera Corporation ...
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... The Test Pattern Generator MegaCore function can generate a user-specified constant ■ color that can be used as a uniform background Preliminary support for Arria II GX devices ■ How to Contact Altera To locate the most up-to-date information about Altera products, refer to the following table. Contact Technical support Technical training Product literature ...
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... Info–2 Contact (Software Licensing) Note to Table: (1) You can also contact your local Altera sales office or sales representative. Typographic Conventions The following table shows the typographic conventions this document uses. Visual Cue Bold Type with Initial Capital Letters bold type Italic Type with Initial Capital Letters ...