IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 174

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

6–18
Table 6–14. Gamma Corrector Signals (Part 2 of 2)
Interlacer
Table 6–15. Interlacer Signals (Part 1 of 2)
Video and Image Processing Suite User Guide
din_startofpacket
din_valid
dout_data
dout_endofpacket
dout_ready
dout_startofpacket
dout_valid
gamma_lut_av_address
gamma_lut_av_chipselect
gamma_lut_av_readdata
gamma_lut_av_write
gamma_lut_av_writedata
clock
reset
control_av_address
control_av_chipselect
control_av_readdata
control_av_waitrequest
control_av_write
Signal
Signal
Table 6–5
shows the input and output signals for the Interlacer MegaCore function.
Direction
In
In
In
In
Out
Out
In
Direction
In
In
Out
Out
In
Out
Out
In
In
Out
In
In
The main system clock. The MegaCore function operates on the rising edge
of the clock signal.
The MegaCore function is asynchronously reset when reset is asserted
high. The reset must be de-asserted synchronously with respect to the
rising edge of the clock signal.
control slave port Avalon-MM address bus. Specifies a word offset into
the slave address space.
control slave port Avalon-MM chipselect signal. The control port
ignores all other signals unless this signal is asserted.
control slave port Avalon-MM readdata bus. These output lines are used
for read transfers.
control slave port Avalon-MM waitrequest signal.
control slave port Avalon-MM write signal. When this signal is asserted,
the control port accepts new data from the writedata bus.
din port Avalon-ST startofpacket signal. This signal marks the start of
an Avalon-ST packet.
din port Avalon-ST valid signal. This signal identifies the cycles when
the port should input data.
dout port Avalon-ST data bus. Pixel data is transferred out of the
MegaCore function over this bus.
dout port Avalon-ST endofpacket signal. This signal marks the end of
an Avalon-ST packet.
dout port Avalon-ST ready signal. This signal is asserted by the
downstream device when it is able to receive data.
dout port Avalon-ST startofpacket signal. This signal marks the start
of an Avalon-ST packet.
dout port Avalon-ST valid signal. This signal is asserted when the
MegaCore function outputs data.
gamma_lut slave port Avalon-MM address. Specifies a word offset into
the slave address space.
gamma_lut slave port Avalon-MM chipselect signal. The gamma_lut
port ignores all other signals unless this signal is asserted.
gamma_lut slave port Avalon-MM readdata bus. These output lines are
used for read transfers.
gamma_lut slave port Avalon-MM write signal. When this signal is
asserted, the gamma_lut port accepts new data from the writedata bus.
gamma_lut slave port Avalon-MM writedata bus. These input lines are
used for write transfers.
(1)
(1)
Description
Description
January 2011 Altera Corporation
(1)
(1)
Chapter 6: Signals
(1)
Interlacer