IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 182

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

7–2
Table 7–2. Alpha Blending Mixer Control Register Map
Clipper
Table 7–3. Clipper Control Register Map (Part 1 of 2)
Video and Image Processing Suite User Guide
0
1
2
3
4
5
Note to
(1) The value of this register is checked at the start of each frame. If the register is changed during the processing of a video frame, the change
(2) For efficiency reasons, the Video and Image Processing Suite MegaCore functions buffer a few samples from the input stream even if they are
(3) The rows in the table are repeated in ascending order for each layer from 1 to the foreground layer.
0
1
2
3
4
Address
Address
does not take effect until the start of the next frame.
corresponding layer has been deactivated.
not immediately processed. This implies that the Avalon-ST inputs for foreground layers assert ready high and buffer a few samples even if the
Table
Control
Status
Layer 1 X
Layer 1 Y
Layer 1
Active
Layer 2 X
Register(s)
Control
Status
Left Offset
Right Offset or
Width
Top Offset
7–2:
Register
The width of each register in the Alpha Blending Mixer control register map is 16 bits.
The control data is read once at the start of each frame and is buffered inside the
MegaCore function, so the registers may be safely updated during the processing of a
frame.
Table 7–3 on page 7–2
The control data is read once at the start of each frame and is buffered inside the
MegaCore function, so the registers can be safely updated during the processing of a
frame. Note that all Clipper registers are write-only except at address 1.
Bit 0 of this register is the Go bit, all other bits are unused. Setting this bit to 0 causes the Alpha
Blending Mixer MegaCore function to stop the next time control information is read. Refer to
“Avalon-MM Slave Interfaces” on page 4–17
Bit 0 of this register is the Status bit, all other bits are unused. Refer to
Interfaces” on page 4–17
Offset in pixels from the left edge of the background layer to the left edge of layer 1.
Offset in pixels from the top edge of the background layer to the top edge of layer 1.
Layer 1 is displayed if this control register is set to 1. Data in the input stream is consumed but
not displayed if this control register is set to 2, Avalon-ST packets of type 2 to 14 are still
propagated as usual. Data from the input stream is not pulled out if this control register is set to
0. (1), (2).
….
(3)
Bit 0 of this register is the Go bit, all other bits are unused. Setting this bit to 0 causes the
Clipper MegaCore function to stop the next time control information is read. Refer to
“Avalon-MM Slave Interfaces” on page 4–17
Bit 0 of this register is the Status bit, all other bits are unused. The Clipper MegaCore
function sets this address to 0 between frames. It is set to 1 while the MegaCore function
is processing data and cannot be stopped. Refer to
page 4–17
The left offset, in pixels, of the clipping window/rectangle.
In clipping window mode, the right offset of the window. In clipping rectangle mode, the
width of the rectangle.
The top offset, in pixels, of the clipping window/rectangle.
for full details.
describes the Clipper MegaCore function control register map.
for full details.
(1)
Description
for full details.
Description
for full details.
“Avalon-MM Slave Interfaces” on
(1)
(2)
Chapter 7: Control Register Maps
January 2011 Altera Corporation
“Avalon-MM Slave
(1)
(1)
Clipper