IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 195

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 7: Control Register Maps
Scaler II
Scaler II
Table 7–19. Scaler II Control Register Map (Part 1 of 2)
January 2011 Altera Corporation
0
1
2
3
4
5
6
7
8
9
Address
Control
Status
Reserved
Output Width
Output Height
Horizontal Coefficient
Write Bank
Horizontal Coefficient
Read Bank
Vertical Coefficient Write
Bank
Vertical Coefficient Read
Bank
Horizontal Phase
1
Table 7–18. Example of Using the Scaler Control Registers (Part 2 of 2)
Table 7–19
run-time control register map for the Scaler II MegaCore function is altered and does
not match the register map of the Scaler MegaCore function.
The N
The Scaler II reads the control data once at the start of each frame and buffers the data
inside the MegaCore function. The registers may be safely updated during the
processing of a frame, unless the frame is a coefficient bank.
The coefficient bank that is being read by the Scaler II must not be written to unless
the core is in a stopped state. To change the contents of the coefficient bank while the
Scaler II is in a running state, you must use multiple coefficient banks to allow an
inactive bank to be changed without affecting the frame currently being processed.
Note that all Scaler II registers are write-only except at address 1.
11
12
Address
Register
taps
is the number of horizontal or vertical filter taps, whichever is larger.
describes the Scaler II MegaCore function control register map. The
–8
7
Value
Bit 0 of this register is the Go bit, all other bits are unused. Setting this bit
to 0, causes the Scaler II to stop the next time that control information is
read.
Bit 0 of this register is the Status bit, all other bits are unused. When this
bit is set to 0, the Scaler II sets this address to 0 between frames. It is set
to 1 while the MegaCore function is processing data and cannot be
stopped.
Reserved for future use.
The width of the output frames in pixels.
The height of the output frames in pixels.
Specifies which memory bank horizontal coefficient writes from the
Avalon-MM interface are made into.
Specifies which memory bank is used for horizontal coefficient reads
during data processing.
Specifies which memory bank vertical coefficient writes from the Avalon-
MM interface are made into.
Specifies which memory bank is used for vertical coefficient reads during
data processing.
Specifies which horizontal phase the coefficient tap data in the
Coefficient Data register applies to. Writing to this location, commits
the writing of coefficient tap data. This write must be made even if the
phase value does not change between successive sets of coefficient tap
data.
Setting up Tap 3 for Phase 7.
Commit the writes to Phase 7.
Description
Purpose
Video and Image Processing Suite User Guide
7–15