IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 196

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

7–16
Table 7–19. Scaler II Control Register Map (Part 2 of 2)
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Table 7–20. Switch Control Register Map
Test Pattern Generator
Video and Image Processing Suite User Guide
10
11 to
10+N
0
1
2
3
4
...
15
Address
Address
taps
Control
Status
Output Switch
Dout0 Output Control
Dout1 Output Control
...
Dout12 Output Control
Vertical Phase
Coefficient Data
Register(s)
Table 7–20
The width of each register in the Test Pattern Generator control register map is 16 bits.
The control data is read once at the start of each frame and is buffered inside the
MegaCore function, so that the registers can be safely updated during the processing
of a frame or pair of interlaced fields.
After control data has been read, the Test Pattern Generator MegaCore function
outputs a control packet that describes the following image data packet. When the
output is interlaced, the control data is processed only before the first field of a frame,
although a control packet is sent before each field.
Register
describes the Switch MegaCore function control register map.
Writing a 1 to bit 0, starts the MegaCore function, writing a 0 to bit 0 stops the
MegaCore function.
Reading a 0 from bit 0, indicates that the MegaCore function is running (video
is flowing through it), reading a 1 indicates that it is stopped.
Writing a 1 to bit 0, indicates that the video output streams should be
synchronized and then the new values in the output control registers should
be loaded.
A one-hot value that selects which video input stream should propagate to this
output. For example, for a 3 input switch:
■
■
■
■
As Dout0 Output Control but for output dout1.
...
As Dout0 Output Control but for output dout12.
3'b000 = no output
3'b001 = din_0
3'b010 = din_1
3'b100 = din_2
Specifies which vertical phase the coefficient tap data in the
Coefficient Data register applies to. Writing to this location, commits
the writing of coefficient tap data. This write must be made even if the
phase value does not change between successive sets of coefficient tap
data.
Specifies values for the coefficients at each tap of a particular horizontal
or vertical phase. Write these values first, then the Horizontal Phase
or Vertical Phase, to commit the write.
Description
Description
Chapter 7: Control Register Maps
January 2011 Altera Corporation
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