IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 126

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–46
Table 5–19. Deinterlacer Avalon-ST Video Protocol Parameters
Frame Buffer
Video and Image Processing Suite User Guide
Frame Width
Frame Height
Interlaced /
Progressive
Bits per Color Sample
Color Pattern
Parameter
1
Control packets and user packets are never repeated and they are not dropped or
truncated as long as memory space is sufficient. This behavior also applies for the
parameterizations that do not use buffering in external memory; incoming control
and user packets are passed through without modification.
In all parameterizations, the Deinterlacer MegaCore function generates a new and
updated control packet just before the processed image data packet. This packet
contains the correct frame height and the proper interlace flag so that the following
image data packet is interpreted correctly by following MegaCore functions.
The Deinterlacer uses 0010 and 0011 to encode interlacing values into the Avalon-ST
Video packets it generates. These flags mark the output as being progressive and
record information about the deinterlacing process. (Refer to
The interlacing is encoded as 0000 when the Deinterlacer is passing a progressive
frame through.
The Deinterlacer MegaCore function can process streams of pixel data of the types
shown in
The Frame Buffer MegaCore function buffers progressive or interlaced video fields in
external RAM. When frame dropping and frame repeating are not allowed, the Frame
Buffer provides a double-buffering function that can be useful to solve throughput
issues in the data path. When frame dropping and/or frame repeating are allowed,
the Frame Buffer provides a triple-buffering function and can be used to perform
simple frame rate conversion.
The Frame Buffer is built with two basic blocks: a writer which stores input pixels in
memory and a reader which retrieves video frames from the memory and outputs
them.
Run time controlled. (Maximum value specified in the parameter editor.)
Run time controlled. (Maximum value specified in the parameter editor.)
Interlaced input, Progressive output (plus optional passthrough mode for progressive input).
Number of bits per color sample selected in the parameter editor.
One, two or three channels in sequence or in parallel as selected in the
parameter editor. For example, for three channels in sequence where ,
When the compatibility mode for subsampled 4:2:2 Y’CbCr data is turned on,
the motion-adaptive deinterlacer expects the data as either 4:2:2 parallel data
(two channels in parallel) or 4:2:2 sequential data (two channels in sequence):
can be any color plane:
Table
5–19.
Value
Chapter 5: Functional Descriptions
Table 4–4 on page
January 2011 Altera Corporation
,
and
Cb
α
Cb Cr
Y
Y
Frame Buffer
β
Cr
Y
4–8.)
γ
Y