IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 24

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

1–16
Table 1–18. Interlacer Performance (Part 2 of 2)
Table 1–19. Scaler Performance
Table 1–20. Scaler II Performance (Part 1 of 2)
Video and Image Processing Suite User Guide
Notes to
(1) EP4CGX15BF14C6 devices.
(2) 5SGXEA7H3F35C3 devices.
Scaling 640×480, 8-bit, three color data up to 1,024×768 with linear interpolation. This can be used to convert video
graphics array format (VGA - 640×480) to video electronics standards association format (VESA - 1024×768).
Scaling R’G’B’ QCIF to common intermediate format (CIF) with no interpolation.
Scaling up or down between NTSC standard definition and 1080 pixel high definition using 10 taps horizontally and 9
vertically. Resolution and coefficients are set by a run-time control interface.
Scaling NTSC standard definition (720x480) RGB to high definition 1080p using a bicubic algorithm.
Notes to
(1) EP4CGX22BF14C6 devices.
(2) 5SGXEA7H3F35C3 devices.
Scaling 640×480, 8-bit, three color data up to 1,024×768 with linear interpolation. This can be used to convert video
graphics array format (VGA - 640×480) to video electronics standards association format (VESA - 1024×768).
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Device Family
Device Family
Device Family
Stratix V
Stratix V
Stratix V
Stratix V
Stratix V
Stratix V
Table
Table
Scaler
Scaler II
(2)
(2)
(2)
(2)
(2)
(2)
1–18:
1–19:
(1)
(1)
(1)
(1)
(1)
Combinational
Table 1–19
Combinational
Table 1–20
Combinational
LUTs/ALUTs
LUTs/ALUTs
LUTs/ALUTs
4,048
2,317
1,728
1,030
356
866
634
411
295
977
780
shows the performance figures for the Scaler.
shows the performance figures for the Scaler II.
Registers
Registers
Registers
Logic
1,061
5,243
3,418
2,078
1,225
1,178
Logic
Logic
444
681
485
297
805
417,456
417,152
30,720
30,720
69,444
69,408
30,816
30,816
4,224
4,224
Bits
Bits
Bits
—
Memory
Memory
Memory
M9K
M9K
M9K
—
—
—
—
—
—
—
—
—
—
—
Chapter 1: About This MegaCore Function Suite
(9×9)
(9×9)
(9×9)
—
—
—
—
19
—
—
—
4
8
4
DSP Blocks
DSP Blocks
DSP Blocks
Performance and Resource Utilization
January 2011 Altera Corporation
(18×18)
(18×18)
(18×18)
—
—
—
—
—
19
—
4
8
8
5
338.41
203.67
336.47
354.99
182.95
227.63
203.46
309.98
181.52
279.96
(MHz)
(MHz)
248.2
(MHz)
f
f
f
MAX
MAX
MAX