IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 161

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 6: Signals
Clocked Video Input
Table 6–5. Clipper Signals (Part 2 of 2)
Clocked Video Input
Table 6–6. Clocked Video Input Signals (Part 1 of 3)
January 2011 Altera Corporation
control_av_readdata
control_av_waitrequest
control_av_write
control_av_writedata
din_data
din_endofpacket
din_ready
din_startofpacket
din_valid
dout_data
dout_endofpacket
dout_ready
dout_startofpacket
dout_valid
Note to
(1) These ports are present only if Include Avalon-MM interface is on in the parameter editor.
rst
vid_clk
av_address
av_read
Table 6–5
Signal
Signal
Table 6–6
function.
Direction
In
In
In
In
shows the input and output signals for the Clocked Video Input MegaCore
Direction
Out
Out
In
In
In
In
Out
In
In
Out
Out
In
Out
Out
The MegaCore function is asynchronously reset when rst is asserted high. The
reset must be de-asserted synchronously with respect to the rising edge of the
is_clk signal.
Clocked video clock. All the video input signals are synchronous to this clock.
control slave port Avalon-MM address bus. Specifies a word offset into the slave
address space.
control slave port Avalon-MM read signal. When this signal is asserted, the
control port drives new data onto the read data bus.
control slave port Avalon-MM readdata bus. These output lines are used
for read transfers.
control slave port Avalon-MM waitrequest signal.
control slave port Avalon-MM write signal. When this signal is asserted,
the control port accepts new data from the writedata bus.
control slave port Avalon-MM writedata bus. These input lines are used
for write transfers.
din port Avalon-ST data bus. Pixel data is transferred into the MegaCore
function over this bus.
din port Avalon-ST endofpacket signal. This signal marks the end of an
Avalon-ST packet.
din port Avalon-ST ready signal. This signal indicates when the MegaCore
function is ready to receive data.
din port Avalon-ST startofpacket signal. This signal marks the start of
an Avalon-ST packet.
din port Avalon-ST valid signal. This signal identifies the cycles when the
port should input data.
din port Avalon-ST data bus. Pixel data is transferred out of the MegaCore
function over this bus.
dout port Avalon-ST endofpacket signal. This signal marks the end of an
Avalon-ST packet.
dout port Avalon-ST ready signal. This signal is asserted by the
downstream device when it is able to receive data.
dout port Avalon-ST startofpacket signal. This signal marks the start of
an Avalon-ST packet.
dout port Avalon-ST valid signal. This signal is asserted when the
MegaCore function outputs data.
(1)
(1)
(1)
Description
Description
Video and Image Processing Suite User Guide
(1)
(1)
(1)
6–5